LMK04828 / Can you please provide more detailed info on the primary to secondary ref input failover auto mode?

Elaboration on section 9.3.5.3 Input Clock Switching - Automatic Mode:
Provided that EN_CLKin0 = 1, EN_CLKin1 = 1, and EN_CLKin2 = 0 and HOLDOVER_EN = 0, HOLDOVER_HITLESS_SWITCH = 0, HOLDOVER_PLL1_DET = 0.
Once the device asserts PLL DLD on CLKin0, then upon loss of CLKin0 (DLD goes low), then the device will use CLKin1 as reference and attempt to lock. Until PLL1 is locked to CLKin1, it will remain selecting CLKin1 as input. After PLL DLD is asserted, then if DLD falls again, CLKin0 will be selected for input (no CLKin2 because EN_CLKin2 = 0).

If the HOLDOVER_EN = 1, HOLDOVER_HITLESS_SWITCH = 1, HOLDOVER_PLL1_DET = 1. The device will be in holdover mode after going out of lock while waiting for phase alignment with the newly selected clock. Depending on PPM accuracy to the the new clock (close ppm accuracy with large phase error can result in long switching time to new clock).

73,
Timothy