About output duty cycle of LMK03318

Hi Satoshi,

The duty cycle specification for the LMK03318 outputs specifies a minimum of 45% and a maximum of 55% for all output types.

Regards,
-Tim

Hi Satoshi-san,

Since the LMK03318 outputs have a fast rise/fall time, duty cycle distortion due to the clock buffer should be negligible, assuming proper biasing at the clock buffer input.

The clock buffer output duty cycle will depend on the biasing between the LMK03318 and the clock buffer input. For example, consider the LMK00105 buffer input pins. The differential input pins (CLKin+ and CLKin-) are self-biased with internal weak bias resistors (above 50 kohm range). The offset voltage of ~0.3 V was intentionally designed as a fail-safe mechanism to avoid input switching/chattering when the differential input pins are floating. This sets the inputs to a low logic state when the differential input pins are floating.

Assuming an AC biased input to the clock buffer, the DC blocking capacitors will preserve the input offset voltage and cause the switching threshold to be offset from the 50% level of the input clock, which could lead to the duty cycle distortion. The slower the slew rate of the input clock, the worse the duty cycle distortion. A similar case applies to DC biasing, where the accuracy of the biasing voltage also factors into the switching threshold offset.

With the high performance of the LMK03318 outputs though, these effects should be minimized. See this thread for a discussion on a similar subject: e2e.ti.com/.../531869

Regards,
-Tim