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LMK04803 and LMK04828 Recommendations

Aramis P. Alvarez
Genius 10370 points
Other Parts Discussed in Thread: LMK04828, LMK04803, LMK03328, CDCM6208, LMK04808

Hi Team,

I have a customer that needs to design a data converter clock generator and a JESD204B Sync/Clock controller.  Here's their question:

"I have been looking at the LMK04803 for the clock generator and the LMK04828 for the JESD controller, but they appear to have some limitations with regard to our applications and I’m not sure how they work in some aspects.

Our clock generator requirements specify a minimum of four separate frequency outputs; the LMK04803 can generate six.  Since all outputs are divided from a common VCO output (PLL2), there will be a dependency between them, limiting the different frequencies that can be generated on each output at the same time.  In addition, because the internal VCO has a limited frequency range (1840 to 2030 MHz), it appears that it is not possible to generate all frequencies in the ranges listed in the SCC spec.  For example, it appears it cannot generate frequencies between 676.7 and 920 MHz.  Is this the case?  I’m waiting to find out from our systems engineers if these limitations are an issue, but want to confirm that these are real limitations (Web Bench appears to confirm this).  I am confused about the architecture of this part, as it does not appear that the PLL1 loop has any internal VCO.  Is an external VCO required for this PLL?  Could it be used to reduce some of these limitations?  What is the purpose of PLL1?

I don’t yet have the output frequency requirements for the JESD controller, but I have the same confusion about the purpose of PLL1 in the LMK04828.  It looks like it can generate enough separate outputs (again all divided from the PLL2 VCO), but I’m not sure how our JESD SYNC connections will work with this part.  The part has only one SYNC input, but we will have four SYNC outputs from the ASIC and external converters.  Can these SYNC signals be gated into one LMK04828, or will I need to use multiple LMK04828 parts?"


Any guidance would be helpful. Thanks in advance.

-Aramis

  • 0
    TI__Mastermind 28550 points
    Hello,

    The LMK0480x and LMK0482x are dual loop devices. The first loop typically uses an external VCXO with a narrow loop bandwidth to provide jitter attenuation to noise on reference signal or to increase the reference frequency to PLL2 for best noise performance of PLL2. Higher phase detector frequency means lower PLL2 in-band noise. This is why we call it a jitter cleaning configuration. It is not required to use PLL1/VCXO as the first PLL may be powered down and the device used in PLL2 only mode. This is typically called a 'clock generation' mode. Both cases, dual loop and single loop generate clocks. It's also worth noting that anytime a PLL is used, the voltage controlled oscillator, be it a VCXO or VCO will perform jitter cleaning above the loop bandwidth, but the PLL1 with the external VCXO is typically designed with a very narrow loop bandwidth which permit it to clean jitter to lower offsets. It's common use case is to accept a recovered clock from a SERDES device which is in need of 'jitter cleaning.'

    Refer to the "Choosing PLL loop bandwidths" presentation in the files section of the clocking e2e site.

    Due to the integer nature of the PLL N and the integer output dividers, you're correct that the output frequencies need to be related such that a single VCO frequency can produce all required clocks with integer dividers. We offer 4 flavors of LMK0480x and 3 flavors of LMK0482x to give a variety of frequency options. Take note our CDCM6208 device (single loop, integer PLL) has fractional output dividers and the LMK03328 has two fractional PLLs to allow for increased output frequency flexibility of non-related output frequencies.

    As for JESD204B with LMK0482x. The key item is the large divider 8 to 8191 with the ability to generate a series of pulses to reset the LMFC in the target JESD204B devices. Use case is to synchronize all the dividers with each other on the LMK0482x (not related to JESD204B, can be done by software), then when the device sends the SYSREF pulses, then all devices attached get reset at a deterministic time. If more than one LMK0482x is being used, then you may need to sync the LMK0482xs together. For this I typically recommend using the CLKin0 path which can route to the SYNC/SYSREF path and is a high performance path. I'm currently working on an app note regarding multi-LMK0482x sync.
    - If you want another device to be a SYSREF master, that is possible, I suggest setting the device for 0-delay mode, program the SYSREF divider to produce a frequency same as your reference frequency. Then select the Re-clocked SYNC/SYSREF option for SYSREF_MUX. This will allow you to send a signal into CLKin0 with respect to your reference, and have it re-clocked to the VCO clock domain for distribution with delay adjusts, etc. to the LMK0482x target devices.

    73,
    Timothy
  • 0
    TI__Mastermind 28550 points
    You are correct about the 676.7 to 920 MHz hole from LMK04803. Because 1840 MHz / 2 = 920 MHz and 2030 / 3 = 676.667 MHz, there is a hole. Now the LMK04808 for instance tunes 2750 to 3072 MHz, this gives you coverage from 687.5 to 768 MHz (/4) and 916.667 to 1024 MHz (/3). Other LMK0480x devices will provide slightly different coverage based on their VCO frequencies.

    The LMK0482x is in the same situation, except it has two internal VCOs, this gives you more frequency coverage, similar to having two LMK0480x, but does not allow two VCOs to be used at the same time.

    73,
    Timothy
  • 0 in reply to Timothy T
    Prodigy 20 points
    Timothy, Hello and thanks for the previous replies. My customer has even more questions if you're up for it!

    1. I hate to pile on the questions, but my schedule is short and I keep finding new uncertainties in their data sheet. I’m now looking at power connections and current consumption per Figure 40 and Table 127. I’m splitting the power up per Figure 40 (generally), and so need to determine individual power pin currents to properly size beads. My main question is – How do the currents listed in Table 127 relate to the separate power pins?

    There are six clock output power pins, one for each of the six clock groups. Are the currents listed under Clock Output Buffers on page 128 the currents (and the only currents) I would expect on these six clock output power pins (pins 17, 18, 47, 52, 57 and 64)? If I had only two outputs active and both were on clock group 0 as LVDS (pins 1-2 and pins 3-4), would my current on pin 64 be 2 x 14.3 mA typ? If not using any other outputs (and disabling them), I assume the current for the other five output-related VCC pins would be zero.

    Could I then assume that all the remaining currents listed in Table 127 (Core and Functional Blocks) would go into the remaining eight VCC pins in the LMK04803? Would that also include the currents listed on page 127 as “CLKout Group” and “Clock Divider/Digital Delay”, or would these items apply to the six clock output VCC pins?

    Here is another batch of LMK04803 questions:

    1) Section 9.1.2 of the data sheet is listed as “Driving CLKin and OSCin Inputs”, yet only CLKin inputs are mentioned in the sub sections. Does the information in 9.1.2.1 and 9.1.2.2 also apply to OSCin, or only to the CLKin inputs?

    2) If, as I am hoping, that section 9.1.2.2 applies to the OSCin input, then there is conflicting information for OSCin. Section 9.1.2.2 states in two places that “either DC coupling or AC coupling may be used”, but section 8.3.3.2 says the OSCin input “must be AC coupled”. Which is correct for OSCin?

    3) Pin 27, Status_Holdover, is listed as an I/O pin on page 5 of the data sheet. Table 60 (page 76) shows only output types (no input types) for the HOLDOVER_TYPE. How does pin 27 become an input? Can pin 27 be set as an input, or is the information on page 5 in error?

    4) Pin 33, Status_LD, is listed as an I/O pin on page 5 of the data sheet. Table 54 (page 74) shows only output types (no input types) for the LD_TYPE. How does pin 33 become an input? Can pin 33 be set as an input, or is the information on page 5 in error?

    5) Figure 9 on page 23 shows a Microwire readback waveform that does not appear to tri-state. Does the pin configured for readback tri-state when the Microwire enable is inactive, or is this pin actively driving all the time? If it drives all the time, it will not be able to share the control bus with another device, which is a concern for us.


    Here is batch of LMK04803 questions #3, dealing with their supply current calculations.

    6) I think there may be an error in the example current calculation at the bottom of page 126 of the data sheet. I believe they left off the “CLKout Group” current in Table 127 of 2.8 mA, so their total should be 230.9 mA in this example, not 228.1 mA. Am I correct?

    7) Their simplistic example on page126 only uses one output group. If the example were for all outputs as LVDS, I believe that would mean the “CLKout Group” current of 2.8 mA gets added in six times (once for each clock group), the “Clock Divider/Digital Delay” current of 25.5 mA gets added in six times, and the “LVDS” current of 14.3 mA gets added in 12 times (for each of 12 outputs). Is that correct? I think that is correct, as using this methodology give me something pretty close (498.7 mA) to the 505 mA they list for typical current on page 7.


    Thanks!