CDCE72010 PLL fails to lock on FMC150 board after previously working

Joe Kujawski

Other Parts Discussed in Thread: CDCE72010

I had a PLL design that previously worked (see the thread 'CDCE72010 PLL fails to lock on FMC150 board'), but the design stopped working after a few weeks. I checked the board for signs of damage near the VCXO and there does not seem to be an issue. The original (working) register settings for an external 10MHz clock source were as follows:

Reg 0 = 683C038
Reg 1 = 6800002
Reg 2 = 8380000
Reg 3 = 6800002
Reg 4 = E980000
Reg 5 = 6800000
Reg 6 = 6800000
Reg 7 = 8380001
Reg 8 = 6800001
Reg 9 = 68050CC
Reg A = 02FC07C
Reg B = 00001C8
Reg C = 0000180

I have also tried these settings:

reg[0x0] = 0x683C0F8;
reg[0x1] = 0x6800002;
reg[0x2] = 0x8380000;
reg[0x3] = 0x6800002;
reg[0x4] = 0xE980000;
reg[0x5] = 0x6800000;
reg[0x6] = 0x6800000;
reg[0x7] = 0x838003A;
reg[0x8] = 0x6800001;
reg[0x9] = 0x68050CC;
reg[0xA] = 0x0BFC07C;
reg[0xB] = 0x0000080;
reg[0xC] = 0x0000180;

Both of which work in the spreadsheet, but not on the real board.

Any suggestions on how to debug this problem?

-Joe Kujawski

over 9 years ago

0 Madhu Balasubramanian over 9 years ago

TI__Expert 4400 points

The registers look ok to me. Is the problem you see that the PLL is not locked? Can you share the external loop filter components?

0 Joe Kujawski over 9 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

Madhu,

1) Yes, the problem is that the PLL fails to lock.

2) The FMC150 board schematic claims the following values (resister values have been confirmed):

R2 = 4.7K ohms
R3 = 160 ohms
C1 = 100nF
C2 = 22uF
C3 = 100nF

-Joe Kujawski

0 Madhu Balasubramanian over 9 years ago in reply to Joe Kujawski

TI__Expert 4400 points

I'm using a Kvco = 0.02 MHz/V and a desired loop bandwidth of < 100 Hz.

Please try the following:

C1 = 1 nF

R2 = 60 kohms

C2 = 100 nF

R3 = 1 kohm

C3 = 4.7 nF

0 Joe Kujawski over 9 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

Madhu,

Changing these components requires me to modify an OEM board which could be done with considerable effort, but is not the ideal solution. Is there a set of settings that works with the current as-installed components.

-Joe Kujawski

0 Madhu Balasubramanian over 9 years ago in reply to Joe Kujawski

TI__Expert 4400 points

Hi Joe, Can you please send over the VCXO datasheet? I would like to recommend fewest changes possible and if any, just register changes. Thanks.

0 Joe Kujawski over 9 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

The VCXO is VS705 ECE-KAAN 491M520. Data sheet can be found here: www.vectron.com/.../VS705.pdf

Please note that the PLL should lock to both 10MHz and 100MHz. However, if both are not possible, it must lock to a 10MHz source.

Thanks,

-Joe Kujawski

0 Madhu Balasubramanian over 9 years ago in reply to Joe Kujawski

TI__Expert 4400 points

Hi Joe, The Kvco of the Vectron VCXO is 0.2187kHz/V. In other words, your existing loop filter should work fine. There is no need to change the components. The register settings also look ok. Are you able to see an unlocked divided down frequency of the VCXO at the outputs? Have you also probed the LVCMOS input into the CDCE72010? Can you also send over the waveform of the VCXO and input clocks that you probe?

0 Joe Kujawski over 9 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

Pin 62:

Pin 61:

Pin 59:

Pin 58:

Pin 53:

Pin 51:

Please let me know if you need additional measurements.

0 Madhu Balasubramanian over 9 years ago in reply to Joe Kujawski

TI__Expert 4400 points

Hi Joe, You shared earlier the register settings programmed into CDCE72010 which shows secondary input is selected and both input buffers are set to LVCMOS. But your waveforms of secondary input shows much lower amplitude and won't trigger properly for a LVCMOS input since the swing isn't high enough. Vil should be 0.3xVcc and Vih should be 0.7xVcc.

Also the waveforms show 5MHz. Is the input 5Mhz or 10MHz?

0 Joe Kujawski over 9 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

Madhu,

1) I did notice that the input waveform is not as high as it should be which is probably the source of the problem. The source is set to greater than 1Vp-p, so I was surprised to see that the input is so dramatically attenuated. I am looking into this in more detail and will get back in touch if it turns out the issue still exists after the correct voltage is present on the input to your chip.

2) If you double check the plots you will see that the input frequency is 10MHz, so yes, the intent is for this signal to be 10MHz.

-Joe Kujawski

0 Joe Kujawski over 9 years ago in reply to Joe Kujawski

Intellectual 270 points

Madhu,

I have a new board with the secondary inputs that measure between 1.0V and 1.75V. This signal level is too low for the CMOS mode (as you previously indicated), so I tried LVPECL with the following settings:

[REGISTERS]
REG0=683C0F90
REG1=68000021
REG2=83800002
REG3=68000023
REG4=E9800004
REG5=68000005
REG6=68000006
REG7=838003A7
REG8=68000018
REG9=68050CC9
REG10=0BFC07CA
REG11=0000080B
REG12=0000180C

Again the design is failing to lock. Please advise.

-Joe Kujawski

0 Madhu Balasubramanian over 9 years ago in reply to Joe Kujawski

TI__Expert 4400 points

Hi Joe,

Are you AC coupled on the secondary input? The settings require the input section (both P and N) to be AC coupled before the input pins.

0 Joe Kujawski over 9 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

Madhu,

I am not sure if the chip would consider this AC or DC:

0 Joe Kujawski over 9 years ago in reply to Joe Kujawski

Intellectual 270 points

Here is the other part of the input circuit:

0 Madhu Balasubramanian over 9 years ago in reply to Joe Kujawski

TI__Expert 4400 points

Hi Joe, The LVPECL input has a 50 ohm to Vbb (1.9V) all on-chip. So can you remove R50 and R51?

0 Joe Kujawski over 9 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

Madhu,

The board is a COTS board. While I can remove these parts, I am really looking for a way to run it as-is. Should I use LVDS instead?

0 Madhu Balasubramanian over 9 years ago in reply to Madhu Balasubramanian

TI__Expert 4400 points

In this case, you can try the following. Please set REG1=68000061

0 Joe Kujawski over 9 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

Madhu,

The pll *does not* lock with the following register settings:

reg[0x0] = 0x6800006;
reg[0x1] = 0x6800002;
reg[0x2] = 0x8380000;
reg[0x3] = 0x6800002;
reg[0x4] = 0xE980000;
reg[0x5] = 0x6800000;
reg[0x6] = 0x6800000;
reg[0x7] = 0x838003A;
reg[0x8] = 0x6800001;
reg[0x9] = 0x68050CC;
reg[0xA] = 0x0BFC07C;
reg[0xB] = 0x0000080;
reg[0xC] = 0x0000180;

Input to CDCE72010 pin 61&62 is a sine at 10MHz from 1.7 to 2.1V.

0 Joe Kujawski over 9 years ago in reply to Joe Kujawski

Intellectual 270 points

It also *does not* lock with these settings:

reg[0x0] = 0x683C0F9;
reg[0x1] = 0x6800006;
reg[0x2] = 0x8380000;
reg[0x3] = 0x6800002;
reg[0x4] = 0xE980000;
reg[0x5] = 0x6800000;
reg[0x6] = 0x6800000;
reg[0x7] = 0x838003A;
reg[0x8] = 0x6800001;
reg[0x9] = 0x68050CC;
reg[0xA] = 0x0BFC07C;
reg[0xB] = 0x0000080;
reg[0xC] = 0x0000180;

Input to CDCE72010 pin 61&62 is a sine at 10MHz from 1.7 to 2.1V.

0 Madhu Balasubramanian over 9 years ago in reply to Joe Kujawski

TI__Expert 4400 points

Hi Joe,

The input swing is 0.4V in half clock cycle (50ns) and the input slew rate is 0.008 V/ns.

This is going to be a problem. The datasheet of CDCE72010 on page 8 shows that the minimum slew rate on secondary input is 1 V/ns. If it is lower, the secondary input won't be recognized as a valid input and PLL won't be locked.

Can you look at way of increasing input slew rate?

0 Joe Kujawski over 9 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

Madhu,

I changed the slew rate per the attached scope plot. Still no luck getting the PLL to lock.

0 Madhu Balasubramanian over 9 years ago in reply to Joe Kujawski

TI__Expert 4400 points

hi Joe, I am unclear why there is still no PLL lock. I have asked my colleague to take a look at it since I am out of office till Sep 12. We will get back to you shortly.

0 Joe Kujawski over 8 years ago in reply to Madhu Balasubramanian

Intellectual 270 points

This issue is still not resolved and the time it is taking to resolve the issue/ask questions and get responses is unacceptably long. At this point in time, I am willing to continue working the issue, but have started to redirect my efforts to eliminate this particular TI part from the design.

0 Tim Chao Li over 8 years ago in reply to Joe Kujawski

TI__Expert 4415 points

Hi Joe,

Thanks for your patience. We've been testing out your configurations and think we may have found a bug that is causing this issue. It looks like when the reference input select is set to Secondary, the device will sometimes not detect an input, which explains why your original configuration was working but then stopped working. The workaround is to set the input select to 'Auto' by setting bits 2 and 3 of Register 0 both to 1. So the only change to your original register settings would be to register 0. The updated settings are as follows:

Reg 0 = 683C03C

Reg 1 = 6800002

Reg 2 = 8380000

Reg 3 = 6800002

Reg 4 = E980000

Reg 5 = 6800000

Reg 6 = 6800000

Reg 7 = 8380001

Reg 8 = 6800001

Reg 9 = 68050CC

Reg A = 02FC07C

Reg B = 00001C8

Reg C = 0000180

Let me know if this solves the issue.

Regards,

-Tim

0 Joe Kujawski over 8 years ago in reply to Tim Chao Li

Intellectual 270 points

Tim,

Thanks for looking into this. So far these alternate settings have worked in a continuous 7 hour run. I think that this solves the issue.

-Joe Kujawski

Clock & timing

Clock & timing forum

CDCE72010 PLL fails to lock on FMC150 board after previously working