CDCE72010 Coarse Phase Adjust Register - Bits (PH#ADJC#)

Simon D.

Other Parts Discussed in Thread: CDCE72010, ADS62P49

Hello,

J'd like to clock the TI ADC ADS62P49 with a frequency of 250 MHz clock with low jitter. Therefor I use the CDCE72010 chip with an 250 MHz VCXO and an 25 MHz reference oscillator.

I' ve read the whole datasheet but have still one question:

The Output-Register-Bits from 6 to 12 (PH#ADJC#) are to select the "Coarse Phase adjust" for each output channel. But where can I find the table with values I have to write to this register-bits? In the datasheet, page 59, stands: For a complete listing of the coarse phase adjust settings, refer to the CDCE72010 Coarse Phase Adjust" document. But I cant find this document...

I' d like to set the output divider to 1 and 0 degree phase shifting...

Refer to page 34 of the datasheet, to set output divider to 1, I have to write 0100000 in the Output Register Bit 13 - 19. In this table stands, that with divider 1 the phase shifting is 0 degree.... but why are there extra PH#ADJC# Bits???

Regards Simon

over 15 years ago

0 Madhu Balasubramanian over 15 years ago

TI__Expert 4400 points

The phase adjust function on CDCE72010 will depend on the output divider and VCXO frequency that are chosen. The number of phase adjust steps is determined by the output divider value (including the default) and step size is determined by the period of the VCXO clock. When using an output divider of 1, there is only the default setting and no ability to shift out the phase.

The additional bits that you mention are for shifting the phase of the clock with respect to the default for a higher output divide value.

Clock & timing

Clock & timing forum

CDCE72010 Coarse Phase Adjust Register - Bits (PH#ADJC#)