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7.5GHz synthesizer using LMX2592

Moti Kabelly
Prodigy 10 points
Other Parts Discussed in Thread: LMX2592

The synthesizer requirements:

7.5GHz, Phase Noise requirements: 100Hz -73, 1KHz -95, 10KHz -99, 100KHz -104

I would like to use low PN 100MHz XO (assume low enough for the app).

Can I use 10MHz Reference (100MHz/10) and fraction of 0.1x. Ie. resolution of 1MHz. What loop BW is needed.

I also need spurs -50dbc + margin

Can I get the PN and spurs performance with these settings. If not what reference is needed to get the PN.

The DS have better performance plot Fig 33 at 6GHz. What is the XO, REF, loop BW and other setting to generate that signal. Fractional or fixed.

TX

Moti

  • 0
    TI__Expert 8495 points
    Moti,

    The PLLatinum is the perfect tool for you:

    www.ti.com/.../pllatinumsim-sw

    You can simulate the phase noise you get at various configurations. spurs will also be broken down into the different types.

    For your use case you will want to find a 100MHz XO that is below your require phase noise level when converted to 7.5GHz. Essentially, the 100MHz noise will convert by 20*log(7500/100), which is 37.5dB. The LMX2592 PLL noise is about -98dBc/Hz at 1kHz offset, so you want to try to find a 100MHz XO that is below -135dBc/Hz at kHz offset or the XO noise will dominate. Similarly for the other offsets.

    Figure 33 follows the same guidelines. It uses a 100MHz XO that is much lower noise than the LMX2592 PLL noise so it doesnt contribute. Then it uses the doubler in the input path for a 200MHz PFD, theoretically lowering PLL noise floor by 3dB. its a integer mode setting using a 6GHz VCO. Loop filter designed for about 150kHz offset for best jitter. The simulation tool can also let you optimize for different preferences of your design.

    regards,

    Brian Wang