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CDCE62002 Power usage

Neil Hinckley
Prodigy 30 points

How is the power usage distributed between the digital and analog rails on this chip? I would assume that the analog supply needs to supply the majority of the ~300mA needed, but I can't find anything on the datasheet that specifies this.

  • 0
    TI__Expert 4415 points

    Hi Neil,

    Page 37 of the datasheet lists a chart of the power dissipation of the various blocks in the device. Using that and the Pin Functions table on page 3 (which lists which power pins are analog and which are digital) we can make a rough estimate of the power distribution between the analog and digital rails.

    There are 2 outputs and each is either a single differential output or 2 LVCMOS outputs, so the output buffer current consumption can be calculated accordingly.

    Assuming a worst case current consumption scenario with both outputs set to LVPECL, and assuming that the PLL current consumption is evenly divided between analog and digital (the exact current distribution has not been characterized), the analog current consumption is 9.70+50.46=60.16mA. The digital current consumption is 50.46+55.76+90.91=197.13mA.

    Regards,

    -Tim