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Hi Team,
The CDCM6208 has Smart Mux function. From the description, the Primary and Second input can auto change. So we want to know, for the 'smart lock', it will determine the MUX depend on the whether the input clock is exist or not. Or depend on whether the output PLL unlock or not?
When one channel clock disappear, when the Smart Mux change one channel to another. Does it will influence the output clock?
Thank you.
BR
Frank
Hello Frank,
the "smart mux" checks if the primary reference input has a continuously toggling clock. When it stops toggling, it will switch to the secondary reference clock. This will keep the amount of missing clock cycles to a minimum. This can lead to a PLL unlock. Therefore it is important to design the PFD update frequency and the closed loop bandwidth accordingly. The feedback loop should update so slowly, so that it does not see the switch between the two references. Ideally there is only an analog phase pull, but no frequency unlock.
The LOS status signal and bit will show which of the input reference are deemed "active".
Best regards,
Patrick
Hello Frank,
you can find a general description how to optimize PLL circuits here: http://www.ti.com/tool/pll_book
For CDCM6208 you can use Webench or the EVM GUI. Both include phase noise simulation.
Webench will recommend a setting for best phase noise performance.
For help to design the clean switch-over, the customer needs to provide some specs what timing they can tolerate in the system.
Best regards,
Patrick