LMK04828 dual loop mode RB_PLLX_LD_LOST clearing issue

Sergio Fa

Hi team,

we're working with a ctm willing to use ourLMK04828. Currrently they have some technical questions as described below.

"..We are operating the LMK in DUAL loop modus.

CLKin of PLL1 is a 10-MHz oscillator (T604-010.0M) and we use a VCXO (ABLNO-V-80.00-T2) connected via charge pump exit CPout1 and OSCin.

Configuration of PLL1 and PLL2 is according to the attached .sav file.

We start the LMK with register settings according to block “Initial” in attached file LMKRegisterSettings.txt.

After setup we synchronize clocks DCLKout6, DCLKout10, DCLKout12 according to block “Sync” in attached file, applying a fixed digital delay.

When running the LMK we wanted to read back lock information from registers 0x182 and 0x183.

However we did not succeed in clearing RB_PLLX_LD_LOST by setting bit CLR_PLLX_LD_LOST to 1 and then to 0.

Setting CLR_PLLX_LD_LOST this way did not have any effect on RB_PLLX_LD_LOST. Once RB_PLLX_LD_LOST is set by LMK, it cannot be cleared any more.

The source code by which we read back and write the registers is attached in file check_pllx_status.c. Routine check_pllx_status is called every n milli seconds. We tried n=1, 10, 100 without success.."

Thx in advance for kind support and BR

Sergio

lmk_cfg001_20160822.zip

over 9 years ago

0 Julian Hagedorn over 9 years ago

TI__Mastermind 20900 points

Hello Sergio,

i am looking into it.

regards,
Julian

0 Klaus Pfaffelmoser over 9 years ago in reply to Julian Hagedorn

Prodigy 10 points

Hello Sergio, hello Julian,

hereby I provide the content of files LMKRegisterSettings.txt and check_pllx_status.c, mentioned in the first input of Sergio:

LMKRegisterSettings.txt:
*************************************
Initialization:
0x000000
0x000010
0x000200
0x010003
0x010155
0x010301
0x010402
0x010500
0x0106F9
0x010700
0x01080C
0x010955
0x010B00
0x010C02
0x010D00
0x010EF9
0x010F00
0x011002
0x011155
0x011300
0x011400
0x011500
0x0116F1
0x011701
0x011800
0x011900
0x011B00
0x011C02
0x011D00
0x011E71
0x011F01
0x012008
0x012155
0x012300
0x012402
0x012500
0x0126F9
0x012700
0x012800
0x012900
0x012B00
0x012C02
0x012D00
0x012E71
0x012F05
0x013000
0x013100
0x013300
0x013402
0x013500
0x013671
0x013701
0x013800
0x013900
0x013A00
0x013BF0
0x013C00
0x013D08
0x013E01
0x013F00
0x014009
0x014100
0x014200
0x0143DD
0x014497
0x01457F
0x014602
0x01471B
0x014831
0x014900
0x014A02
0x014B0E
0x014C00
0x014D00
0x014E00
0x014F7F
0x015001
0x015102
0x015200
0x015300
0x015401
0x015500
0x015601
0x015700
0x015801
0x015900
0x015A08
0x015BDF
0x015C20
0x015D00
0x015E00
0x015F0B
0x016000
0x016101
0x016224
0x016300
0x016400
0x01650C
0x0171AA
0x017202
0x017C15
0x017D33
0x016600
0x016700
0x01680F
0x016959
0x016A08
0x016B00
0x016C00
0x016D00
0x016E13
0x017300
0x1FFD00
0x1FFE00
0x1FFF53

Clock sync:
0x0143F1
0x0143D1
0x011EF1
0x012EF1
0x0136F1
0x0144FF
0x0143F1
0x0143D1
*************************************

check_pllx_status.c
*************************************
uint32_t c_config_readClockDist[]={
0x18200,
0x18300};

int32_t nr_readClockDist = sizeof(c_config_readClockDist) / sizeof(uint32_t);
uint32_t readback_clockDist[sizeof(c_config_readClockDist) / sizeof(uint32_t)];

void check_pllx_status(void)
{
uint8_t i;

MSS_SPI_configure_master_mode( &g_mss_spi1, actual.hdw.clockDist.noCS, actual.hdw.clockDist.modeSPI, 16u, MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE * 3 );
MSS_SPI_set_slave_select(&g_mss_spi1, actual.hdw.clockDist.noCS);

// read back registers
for(i=0; i<nr_readClockDist;i++){
readback_clockDist[i]=0;
readback_clockDist[i]=MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[i] | 0x800000 );
}
// set CLR_PLLX_LD_LOST to 1
if(readback_clockDist[0] & 0x4)
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[0] & 0x1 );
if(readback_clockDist[1] & 0x4)
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[1] & 0x1 );

// evaluation of registers
....

// set CLR_PLLX_LD_LOST to 0
if(readback_clockDist[0] & 0x4)
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[0] );
if(readback_clockDist[1] & 0x4)
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[0] );
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[1] );

MSS_SPI_clear_slave_select(&g_mss_spi1, actual.hdw.clockDist.noCS);
}

0 Shawn Han over 8 years ago in reply to Klaus Pfaffelmoser

TI__Genius 9920 points

HI Klaus,

Could you help clarify below code if I understood them wrong?

// set CLR_PLLX_LD_LOST to 1
if(readback_clockDist[0] & 0x4)                                                                                 // Shawn: If RB_PLL1_LD_LOST =1
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[0] & 0x1 );       // Shawn: Set CLR_PLL1_LD_LOST =1
if(readback_clockDist[1] & 0x4)                                                                                 // Shawn: If RB_PLL2_LD_LOST =1
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[1] & 0x1 );       // Shawn: Set CLR_PLL2_LD_LOST =1

// evaluation of registers
....

// set CLR_PLLX_LD_LOST to 0
if(readback_clockDist[0] & 0x4)                                                                                 // Shawn: If RB_PLL1_LD_LOST =1 ??? RB_PLL1_LD_LOST had been cleared with // set CLR_PLLX_LD_LOST to 1
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[0] );                 //
if(readback_clockDist[1] & 0x4)
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[0] );
MSS_SPI_transfer_frame( &g_mss_spi1, c_config_readClockDist[1] );

MSS_SPI_clear_slave_select(&g_mss_spi1, actual.hdw.clockDist.noCS);

I think “// set CLR_PLLX_LD_LOST to 1 then to 0” could be combined together.

“To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0.”

Regards,

Shawn

Clock & timing

Clock & timing forum

LMK04828 dual loop mode RB_PLLX_LD_LOST clearing issue