LMK00105 - differential input termination #2

Hiroshi Katsunaga

Mastermind 6480 points

Other Parts Discussed in Thread: LMK00105

Hello,

My customer has a question about LMK00105.

[Background]

I read the following posts.

* lmk00105 differential input termination

* LMK00105 - CLKin / CLKin* Internal Bias Voltage (This is my post.)

[Q]

Which is your recommendation LMK00105EVM differential input interface or LMK00101EVM differential input interface ?

Their differential level is LVDS.

When they selected the LMK00105EVM interface, the glitch occorred in the output.

When they selected the LMK00101EVM interface, no glitch occorred in the output.

The offset bias voltage of CLKin and CLKin* is for fail safe operation.

Therefore I thought that LMK00105EVM interface is suitable for LMK0010x differential input interface.

<LMK00105EVM : Termination -> AC Coupling>

The glitch occored in the output.

<LMK00101EVM : AC Coupling -> Termination>

No glitch occorred in the output.

Best Regards,

Hiroshi Katsunaga

over 9 years ago

0 Alan O over 9 years ago

TI__Mastermind 32575 points

I see the time division is very long, so I'm wondering if the input clock edge rates are slow. What are the input clock edge rates (rising and falling)?

Alan

0 Hiroshi Katsunaga over 9 years ago in reply to Alan O

Mastermind 6480 points

Hi Alan,

Thank you for your fast response.

Their input slew rate is very slow (0.07V/ns).

I show their input waveforms as follows.

In addition, I show the glidch waveform as follows.

Is this glitch caused by low slew rate input signal ?

It occured in LMK00105EVM input interface, but why did it not occur in LMK00101EVM input interface ?

May it occur in LMK00101EVM input interface ?

Best Regards,

Hiroshi Katsunaga

0 Alan O over 9 years ago in reply to Hiroshi Katsunaga

TI__Mastermind 32575 points

I am checking with the IC designer on the questions.

Please clarify for me:

Did the customer try testing using DC-coupled LVDS interface to the CLKin/CLKin* inputs?

Does this issue occur at nominal operating conditions? Were the AC-coupled input interface tests done on their application board or on TI's eval board?

Alan

0 Alan O over 9 years ago in reply to Hiroshi Katsunaga

TI__Mastermind 32575 points

In addition to the other questions:

Would it be possible for them to probe at the inputs to the LMK00105 at the chip in a single ended and differential fashion?

I need to see if there is anything unusual going on directly on the inputs to the part. Also, probing the power/ground for any glitches may help understand what is happening.

Please also share their full clock schematic.

Alan

0 Hiroshi Katsunaga over 9 years ago in reply to Alan O

Mastermind 6480 points

Hi Alan,

Thank you for your fast response!

I will answer your question by e-mail because I can not share their full schematic in this forum.
Please wait a moment.

Best Regards,
Hiroshi Katsunaga

0 Alan O over 9 years ago in reply to Hiroshi Katsunaga

TI__Mastermind 32575 points

Closing this forum thread, and taking discussion off-line.

Clock & timing

Clock & timing forum

LMK00105 - differential input termination #2