I am trying to get a reliable PLL lock on a cdce72010. To determine a reliable lock, I am checking the "PLL_LOCK" pin out of the device.
My VCXO is 320Mhz 200ppm, my input reference clock is 100 Mhz.
In terms of satisfying the M/N/P divider combinations, there are a lot of possibilities. I have tried:
M = 625
N = 500
P = 4
With these settings, sometimes I would get a lock, and other times I would not.
I tried a different set of values:
M = 10000
N = 1000
P = 32
With these settings, I could never get a lock.
I tried a different set of values:
M = 15
N = 48
P = 1
With these settings, I could never get a lock.
I'm using the CDCE72010 PLL Excel file GUI to check my values. In all 3 scenarios, I get a green "In LOCK" status in the GUI. However, I'm not sure how to interpret the various graphs and plots that are generated.
What other considerations should be made in order to get a reliable and fast PLL lock status?
