clock distribution with external 800 MHz sinusoidal input

Bhupesh Patil

Intellectual 440 points

Other Parts Discussed in Thread: CDCE62005

Requirements: 1. Two ADC clocks Range(20MHz-400MHz) 2. Two DAC clocks 3. Synchronization clock to FPGA

Plz Suggest clock distribution scheme

over 15 years ago

0 Fritz over 15 years ago

TI__Expert 4150 points

How about CDCE62005?

http://focus.ti.com/lit/ds/symlink/cdce62005.pdf

0 Bhupesh Patil over 15 years ago in reply to Fritz

Intellectual 440 points

Thanks Firtz for the reply...

My problem is external input is 800 MHz sinusoidal. With CDCE62005, input can be either LVCMOS, LVPECL or LVDS and limited to 500 MHz to use in PLL -VCO mode.

0 Fritz over 15 years ago in reply to Bhupesh Patil

TI__Expert 4150 points

Hello Bhupesh,

how about adding a divider into the signal path to reduce the 800MHz down to 400MHz? Here is a device that can do this: http://www.ti.com/lit/gpn/cdcm1804

It's going to increase your total device count but should overall work fine. thank you! Fritz

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clock distribution with external 800 MHz sinusoidal input