• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 526 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCLVC1108 output termination advice

Mark Guastaferro
Genius 11645 points
Other Parts Discussed in Thread: CDCLVC1108

Using the CDCLVC1108 to drive 8 output clocks to similar devices. F = 40 MHz. VDD = 3.3V, but receiving devices require clock signal between 1VPP and 2VPP. Trace length is about 100mm (50 ohm). Looking for a low power method to terminate CDCLC1108 outputs.

A simple 50 ohm parallel termination or a Thevenin termination with 100 ohm resistors would reduce the signal level well enough, and this could be AC coupled into the receiving device. But with 8 clocks, thats seems like a lot of current for the driver to be sourcing/sinking.

However, are there lower power alternatives?  For example, could one use a series termination at the driver and then use a higher resistance voltage divider at the far end of the trace to attenuate the signal? If so, would it matter which side of the AC coupling cap the divider sits on? These are point-to-point connections for each driver output.

  • 0
    TI__Mastermind 32575 points

    To minimize power, I agree with using series termination near the driver and then using higher resistance voltage divider at the receiver side to attenuate the signal.  If the receiver has internal input biasing, then place the coupling cap after the voltage divider.  Make sure the voltage divider resistors are small enough to minimize the low-pass filtering effect from the any parasitic cap, but large enough to minimize the DC load current on each driver output.

    Alan