Hello,
We have a setup with several data acquisition cards, each one of them using an LMK04821 to generate and distribute clocks to the ADC and other stuff on board. We need to have a deterministic and known phase relationship between the sampling clocks of all cards. We've set up a test situation to check the LMK's functionality and ability to sync in phase. In this test scenario we have two cards (from the total 5 we have) sharing a common external reference. That reference is provided by a signal generator at 24,576 MHz, goes through a 0 degree signal splitter and through equal length cables to the LMK04821's. We've checked that the phase difference at the reference signal cable ends in this setup is essentially negligible.
The LMK's are configured in 0-delay nested dual loop using the external reference, cleaning it through an VCXO, feeding the on-chip VCO and then dividing to the output signals. We use CLK6 as feedback source for the 0-delay setup. CLK6 and other outputs are also broken out to a connector so we can measure the output clocks of the LMK.
So, we get the LMK's to lock in both PLL's, get the output frequencies we desire as we desire and we can measure the output clocks. Both LMK's are configured equally. If we measure CLK6 outputs, we see that they are frequency locked but there's a slight phase difference between them, with one of the boards leading the other in phase. This phase difference is consistent and always the same even if we power-cycle the boards, reset them, turn off the reference to make them unlock and turn it back on so they relock or anything. It's always the same phase difference. Other clock outputs are also frequency locked and also have a phase difference between them that doesn't vary, if we increase the frequency of these outputs the phase difference seems to linearly increase too by the same factor.
If we pick another two cards they share the same behaviour, frequency locked and always the same phase difference between them. That means that with same input phase no two boards provide the same output phase but they always produce the same no matter what we do, meaning that the relationship between them is predictable and deterministic, but it would need to be calibrated. Is that the normal behaviour?
EDIT: from the input reference connectors to the input of the LMK there is a balun, AC caps and so on. The phase differences we see seem to be large enough to not be mostly caused by phase differences between these components. Also, if we try different splitters we have the phase difference varies a little bit but not enough to make the leading card go lagging or vice versa.
Regards,
David
