We use the CDCE62002 in several places within our system to lock to a high precision LVDS system clock and generate local synchronous clock signals. Previously, we had been DC coupling the LVDS system clock from a low impedance source and the biasing was what we expect for LVDS. A recent architectural change to how clocks are routed through the system has led to AC coupling the LVDS system clock in some places. During design verification, we found the bias levels to be incorrect per the CDCE62002 datasheet and configuring the input buffer to bias at LVDS levels actually biased to LVPECL and vice versa. From what I’ve been able to find on the forums, it appears that this is an error in the TI datasheet, and we weren’t seeing this error previously because the DC bias provided by the low impedance clock source dominated the 5k pull up to the incorrect bias on the CDCE62002. https://e2e.ti.com/support/clocks/f/48/p/465924/1696520#1696520
We’d like help with the following:
1) Can you confirm whether the datasheet is incorrect or not when giving instructions on how to configure Register 0 to set the input Buffer Select to LVDS/LVPECL/LVCOMS?
2) If it is incorrect, is there any plan to update the datasheet or is there some formal documentation of errata of this problem anywhere? Our Quality folks would like us to have more than just a reference to a second hand quote of a TI FAE in a forum.
Thank you!
