Hello
We are using the ADC32RF45 evaluation module to evaluate the ADC32RF45 ADC. The clock source for the ADC32RF45 ADC on this evaluation module is a LMK04828 device to generate SYSREF and an LMX2582 to generate the ADC sample clock. We have configured the evaluation module so that only the LMK04828 is used to generate both the ADC sample clock (at 2949.12MHz) and the SYSREF clock (at 4.608MHz). This is a build option of the ADC32RF45 evaluation module.
We are capturing the data from the ADC and plotting the FFT. Our setup is as follows:
External 10MHz reference input clock
Use on-board 122.88MHz VCXO with LMK04828 to generate 2949.12MHz and 4.608MHz.
942.5MHz input signal, 0dBm
ADC configured for decimate by 4, 1000MHz center frequency
Once the ADC has completed the JESD204B synchronisation, we power down the SYSREF SDCLKout. We then capture the data.
However, what we are seeing is that the SYSREF clock is present as sideband spurs around the ADC input signal. This can be seen in the FFT below:
The frequency spacing of the sideband spurs is related to the SYSREF clock frequency.
We have tried asserting all SYSREF related PD bits. We have also made sure that none of the SDCLKout outputs are enabled. They are all powered down. None had an impact on the sideband spurs above.
The only change which did remove the spurs was to assert SYSREF_PD. This powers down the SYSREF Divider. The FFT for the same configuration with the SYSREF_PD asserted can be seen below:
As you can see, the sideband spurs are gone.
Question 1:
Is this expected behaviour? We are using the ADC32RF45 evaluation module so we don't think this is a fault in the hardware design.
For normal operation this would be fine because at power up we would enable SYSREF, perform the JESD204B synchronisation and then power down SYSREF. These sideband spurs would then not be present.
However, in our final application, we will be synchronising multiple LMK04828 devices across multiple boards. We will be doing this according to the proposed method described in the following E2E post:
https://e2e.ti.com/support/clocks/f/48/p/378164/1332595
In other words, all the LMK04828 devices are configured in 0-delay mode and the SYSREF Divider output is set as the feedback clock to the PLL1 phase detector input and a shared SYSREF signal is used as the reference input across the boards. In this way, the SYSREF outputs across all the LMK04828 devices (across multiple boards) are all perfectly phase aligned.
But this method relies on the SYSREF Divider constanly running because it is the source of the feedback clock in the 0-delay mode.
Question 2:
Is there any way to get around this? The benefit of this method is that it guarantees phase alignment of the SYSREF clocks across multiple boards but at the cost of sideband spurs being visible in the ADC output.
Any feedback would be greatly appreciated.
