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Clock driver

KyuEun Park
Prodigy 60 points
Other Parts Discussed in Thread: OPA625, CDCLVC1310, LMK00101, CDC3RL02

Helo

I'm Mr. Park.

I'm designing clock driver for Rubidium and OCXO clock.

As you know both clock needs realy strict noise and jitter condition.

So I don't consider of cost, I just targeting the performance.

I bought Rubidium and OCXO clock, and highend AV dac.

Rubidium clock outputs 3.6Vpp sine wave with 50ohm out imphedance.

OCXO clock outputs 2.3Vpp sine wave with 50ohm out imphedance.

But my dac requires 1.4~2.8Vpp sinewave or 2.7Vpp square wave with 75ohm imphedance.

Of course I will use $1,500 digital cable to connect it.

I chosed CDCLVC1310 for mux and buffer, and OPA625 for driver.

I'm worry about the CDCLVC1310 to buffer the sine wave.

Is it possible? or should I add another circuit?

And can you recommend any better chipset ?

Woops I cannot upload my circuit diagram, Please let me know how?

Thanks

  • 0
    TI__Mastermind 28550 points

    What is the is the frequency of the Rubidium and OCXO?  10 MHz?

    A 10 MHz sinewave at 3.6 Vpp would have a low slew rate, approximately 0.1 V/ns.  I don't see any specific specifications for slew rate for CDCLVC1310, but typically performance is achieved using a higher slew rate on the order of 1.5 or 2 V/ns.  You can see that the LMK00101 recommends 2 V/ns for best performance.

    Perhaps you can use an op amp to convert from sine to square wave for the clock buffer.


    To upload your circuit, you need to click "use rich formatting," then you can attach a file or image by clicking the paper clip icon or (+image) icon.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 60 points

    Helo

    I added my original simple block diagram.

    At below, the clocks are all 10MHz and have 50 ohm as Rs.

    If I use 100nF (for decoupling) and 50 ohm (for terminate), it would be 1.8Vpp or 1.15Vpp.

    I'm OK to use LMK00101, but I concern that the input is sine wave which does not swing fully between Vcc and gnd.

    Can I input the sine wave directly ?   or should I conver it to square wave ?  

    And at the output I added OPA625 to drive and to covert to 75ohm imphedance.

    One is just to drive current and voltage.

    Other is to convert to square wave 

    Can you recommend any other OP Amp ?

     

    Thanks

  • 0 in reply to KyuEun Park
    TI__Mastermind 28550 points
    Here is a device which may solve your issue, CDC3RL02. It support sine to square wave conversion.

    73,
    Timothy
  • 0 in reply to Timothy T
    Prodigy 60 points

    Sorry. CDC3RL02 does not meet the phase noise spec.

    It has "–149 dBc/Hz at 10-kHz Offset Phase Noise".

    But my Rubidium clock has " <–155 dBc/Hz (10 kHz) " .

     Phase noise (SSB) <–130 dBc/Hz (10 Hz)
                                    <–140 dBc/Hz (100 Hz)
                                    <–150 dBc/Hz (1 kHz)
                                    <–155 dBc/Hz (10 kHz)

    I think CDC3RL02 is not a good solution.

    Can you recommend another circuit ?

    Thanks

  • 0 in reply to KyuEun Park
    TI__Mastermind 24205 points

    Hi,

    How about this device: CDC3S04: www.ti.com/.../cdc3s04.pdf
     
    May not be as good as your source but the additive jitter appears to be better than CDC3RL02

    Regards

    Arvind Sridhar

  • 0 in reply to Timothy T
    Prodigy 60 points

     Hi Timothy T

    If I input sine wave to LMK00101, does it have any problem ?

    I think that it will just output sine wave also.

    Park

  • 0 in reply to KyuEun Park
    TI__Mastermind 32575 points
    You can consider CDCLVC1310 (1:10 LVCMOS fanout buffer) in "XTAL overdrive mode" and drive a sinusoidal signal (up to 2-Vpp max) to the XIN input pin through an AC-coupling cap, like shown in Figure 13 in the datasheet. You may replace the 100-ohm parallel resistors with 50-ohm to GND if that's better for your signal source. CDCLVC1310's XIN input buffer stage has very-low additive jitter in XTAL mode, as indicated by Figure 14, and should work better for low-slew-rate signals compared to the Differential/LVCMOS input buffers on PRI_IN and SEC_IN pins.
  • 0 in reply to Alan O
    Prodigy 60 points

    Helo Alen O

    CDCLVC1310 has low noise at high freq. But not at low freq. like as below table.

    Freq CDCLVC1310 Rubidium Clock
    10Hz -90 -130
    100Hz -118 -140
    1kHz -138 -150
    10kHz -159 -155
    100kHz -169 -

    At above table, the noise of CDCLVC1310 if from Fig.14

    Even at LVCMOS output Charactrtistics, the NF at 10kHz is -145 and it is higher than my clock (-155)

    Do you think it will be better, if I input to Xin ?

    Regards

    Park

  • 0 in reply to KyuEun Park
    TI__Mastermind 32575 points

    We don't have such as rubidium source. I suggest you evaluate it using the EVM with your source.

    What is your system application?  What is the system requirement?  what is the system impact if close-in phase noise requirement is not met?

  • 0 in reply to Alan O
    Prodigy 60 points

    Hello

    My rubidium clock is at below link.

    www.thinksrs.com/.../PRS10m.pdf

    My dac is at below link

    www.esoteric.jp/.../indexe.html

    I just have a plan to input 10MHz clock to my dac without loss.

    As a first, I had input the clock directly, and sound quality was really good.

    But I found that my dac has a problem when it converts the input sine wave to internal square wave.

    So I hope to add convert from sine wave to square wave by adding circuit at the output of my clock.

    This is my aim.

    I'm trying to design the buffer circuit that has one sine wave input from my clock,

    and has two outputs, one is sine wave imphedance and other is square wave with 75ohm.

    I have questions and opinions to discuss you.

    1. If I input sine wave to XIN of CDCLVC1310 , Its output is sine wave or square wae?

       I think it may be sine wave.

       So I consider to add sine to square converter for my square outputs.

       I think I use OPA625 with highin (G=10), it will saturated and changed to square wave.

    2. Is CDCLVC1310 possible to drive 75ohm ?

        I think it is impossible, so I consider OPA625 (G=1.x) to drive.

  • 0 in reply to KyuEun Park
    TI__Mastermind 32575 points
    1. CDCLVC1310 output is a square-wave (as it is rail-to-rail LVCMOS output). It doesn't matter if the input is sine wave. The clock output duty cycle will be determined by the input duty cycle.
    2. I don't think so. 75 ohm to GND is too heavy load for the LVCMOS output, which has +/-24 mA recommended max output current (recommended), and +/-50 mA absolute max output current.