Hello, I am using FPGA to program CDCE937. The clock generator is using 13 MHz as the master clock. I want five 40 MHz, one 100 MHz and one 125 MHz clock. First I program register 06h with a value 80h before programming all the PLL registers and then the same register 06h with a value 81h after PLL programming. The I2C speed is 62.5 KHz. Still the device is not getting programmed in the required configuration. Please let me know where I am getting wrong. The register programming sequence that I am using is attached.
Register Value 00 01 01 00 02 B4 03 05 04 02 05 50 06 80 10 00 11 00 12 00 13 00 14 0D 15 02 16 05 17 00 18 FA 19 06 1A 43 1B C7 1C FA 1D 06 1E 43 1F C4 20 00 21 00 22 00 23 00 24 0D 25 02 26 02 27 00 28 FA 29 06 2A 43 2B C7 2C FA 2D 06 2E 43 2F C4 30 00 31 00 32 00 33 00 34 4D 35 02 36 01 37 00 38 FA 39 03 3A 02 3B 65 3C FA 3D 03 3E 02 3F 64 06 81
