CDCEL949

Hi Sujeeva,

It seems PLL is unlocked caused by wrong configuration. Input signal source should be "LVCMOS".

If input frequency = output frequency= 52.386 MHz, you could set VCO 209.544 MHz by manual.

Regards,

Shawn

HI Shawn,

Customer came back.
The LVCMOS setting didn’t work at all. I would not have expected it to as the TI evaluation board has a 27 MHz crystal connected to the clock pins. Is there any way of interrogating the PLL lock status?

Regards,
Sujeeva

Hi Sujeeva,

Your output spectrum shows like unlock. Please confirm both input frequency and output frequency  are 52.386 MHz.

If they are, try attachment configuration.

CDCE949_In_52M386_Out_52M386.zip

Regards,

Shawn

Hi Shawn,

The input frequency to the device is 27 MHz ie. the crystal fitted by default to the CDCE(L)9xx Performance Evaluation Module.

The device on the evaluation module is the CDCEL949.

See the screenshot below for the full configuration, including input and output frequencies. There are 3 output frequencies.

All the links and jumpers are connected for crystal operation as per the documentation.

Please see the attached screen shot

Regards,

Sujeeva

Hi Sujeeva,

How about 61.41666MHz output from CDCEL949? If it is good, we could know 27MHz crystal and PLL2 works well.

You showed 2 spectrum plots, one is clean 52.386 MHz, another is noisy 52.375MHz. Which one is from Y1 of CDCEL949?

Is the clock tree like 27MHz XTAL -- > CDCEL949 --- > 52.386 MHz --- > DDS --- > 52.386MHz ?

Please clarify it. Thanks.

Regards,

Shawn