CDCE937, channel to channel skew

Shinichi Inoue

Guru 21721 points

Other Parts Discussed in Thread: CDCE706

Dear Specialists,

My customer is evaluating CDCM937, and has a question.

Could you please advise listed below.

---question---

Output Y2 and Y7 has a skew.

A skew is different from moment to moment.

For example, attached waveform is 9ns delay.

Is there any problem?

device setting?

or device design spec?

(setting)

Reference 27MHz input and 74.25MHz output

PLL1 and PLL3 is same setting.

I appreciate your great help.

Best regards,

Shinichi

over 8 years ago

0 Julian Hagedorn over 8 years ago

TI__Mastermind 20900 points

Hello,

there is no synchronization mechanism in this Chip. You could only try to use only a single PLL and route the divided clock to as many outputs as possible (e.g. Y1 to Y5 have same frequency)

CDCE706/906 has a bigger output mux that allows all outputs to be derived from all PLLs.

regards,
Julian

0 Shinichi Inoue over 8 years ago in reply to Julian Hagedorn

Guru 21721 points

Dear Julian

Thank you for your reply.

I see.

The waveform from customer is normal.
He should use single PLL and devide.

If he has an additional question, I'll ask again.

I appreciate your great help.

Best regards,
Shinichi

Clock & timing

Clock & timing forum

CDCE937, channel to channel skew