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Differential clock buffer which supports SSTL, HSTL, and POD interface

Kawai
Guru 19785 points

Other Parts Discussed in Thread: LMK00301, CDCLVP1204

Hello Team,

We are asked for clock buffer which supports SSTL, HSTL, and POD memory interface input.
POD is Pseudo Open Drain interface which seems to be used from DDR4-SDRAM.
Do we have any clock buffer which supports below interfaces ?

INPUT : SSTL, HSTL, POD
OUTPUT : LVDS or LVPECL or LVCMOS

I can find below devices, however, did not know if these can support POD interface for input.

Thanks in advance.

Best Regards,

Kawai

  • 0
    TI__Mastermind 32575 points

    POD12/Class A signaling requires 50-ohm termination to VDDQ = 1.2V.  This termination would need to be external to our clock buffer devices.

    A differential buffer with the following input specs could accept DC-coupled POD signaling with external 50 ohms to VDDQ:

    DC-coupled input:

    • Input common mode voltage of 0.7 * 1.2V = 0.84V typ
    • Input swing voltage swing as high as 1.24 V single-ended (Vid) or 2.48 V differential

    LMK00301 (LMK0030x family) with external termination can support SSTL, HSTL, and POD input signaling.  Other buffers may also support it with external termination followed by input AC coupling and input biasing within the Vicm range.

    Alan

  • 0 in reply to Alan O
    Guru 19785 points
    Hello Alan-san,

    Thank you for the information.

    I would like to clarify the external circuit. Could you please draw us a simple POD input schematic as an example for LMK00301 ?

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Mastermind 32575 points

    POD interfacing to CLKIN input of LMK00301:

    POD_OUT_P>----(Zo=50ohm trace)------o-->CLKIN_P(LMK00301)
                                        |
                                        Rt=50ohm 
                                        |
                          VDDQ=1.2V |---o
                                        |
                                        Rt=50ohm
                                        |
    POD_OUT_N>----(Zo=50ohm trace)------o-->CLKIN_N(LMK00301)

     

    Alan

  • 0 in reply to Alan O
    Guru 19785 points
    Hello Alan-san,

    Thank you very much for the detail information.

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    Guru 19785 points
    Hello Alan-san,

    We have another question from our customer that he is also looking for a device which could support below interface.

    INPUT : LVDS or LVCMOS
    OUTPUT : POD or HSTL or SSTL

    It seems we do not have such device, however, if there is any device, could you please let me know ?

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Mastermind 32575 points
    You can use LVPECL buffer (LMK00301/30x, CDCLVP1204/12xx) and level-translate to interface to HSTL inputs.
    See Figure 8 in this app note: www.ti.com/.../scaa059c.pdf

    Alan
  • 0 in reply to Alan O
    Guru 19785 points

    Hello Alan-san,

    Thank you for the information. We also found this app note and shared with our customer.

    I believe there is no particular device which could translate LVDS or LVCMOS input to POD or HSTL or SSTL output directly from the device.

    Thanks and Best Regards,
    Kawai