LMK3033C OUTPUT FREQUENCY NOT AVAILABLE

selva kumar7

Hi,

I am using LMK3033C in my design. I am planning to generate 25.6MHz output with this PLL. My OSCin freq is:25MHz .

I am programming this device from FPGA with sclk of 1MHz & for LE after loading the each register value kept high for 4us & then kept low for 4us.

GOE pin is in kept high.

CPOUT filter Discrete values are C1 is 39pF , C2 is 2700pF and R2 is 5.6Kohm.

R3 Value is 600 ohms and R4 Value is 200 ohms, C3 = 0, C4 =110pF.

Clarification:

Kindly help any one to resolve the issue.

Please find the PLL register values which i was used:

R0 (INIT) 0x80000100

R0 0x00031400

R1 0x00000101

R2 0x00031402

R3 0x00000103

R4 0x00031404

R5 0x00031405

R6 0x00031406

R7 0x00000107

R8 0x10000908

R9 0xA0022A09

R11 0x0082000B

R13 0x0286403D

R14 0x0800190E

R15 0xC804000F

Regards,

Selva

over 8 years ago

0 Timothy T over 8 years ago

TI__Mastermind 28560 points

Is the SYNC* pin held low? Ensure it is high for output.

Is the CPout voltage ~Vcc/2 or railed high or low?

What is the circuit you are using, some outputs are LVDS and others LVPECL, for LVPECL do you have emitter resistors placed?

73,
Timothy

0 selva kumar7 over 8 years ago in reply to Timothy T

Prodigy 120 points

The Issue was cleared. The FPGA does not properly configure the PLL

0 Timothy T over 8 years ago in reply to selva kumar7

TI__Mastermind 28560 points

Ok thanks for letting us know and I'm glad you're up and operating.

73,
Timothy

0 selva kumar7 over 8 years ago in reply to Timothy T

Prodigy 120 points

The LD pin toggles randomly High to low and low to High, I get the loop filter values from clock design tool only.

CPOUT filter Discrete values are C1 is 39pF , C2 is 2700pF and R2 is 5.6Kohm.

R3 Value is 600 ohms and R4 Value is 200 ohms, C3 = 0, C4 =110pF.

As above mentioned Loop filter values are ok or not ?

Kindly suggest the solution.

Clock & timing

Clock & timing forum

LMK3033C OUTPUT FREQUENCY NOT AVAILABLE