CDCE62005 Question..

Update:

Another characteristic the customer is noticing is that their supply is not monotonic and that it actually progressively steps up as other supplies turn on (supply to synthesizer is turned on by FET). They were able to reduce the turn-on time from when the main 3.3V supply turns on to when the supply to the synthesizer turns on (please see scope shots below, first is long power up, second is short) but I’m guessing this could still be a cause of the instability/loss of lock they’re seeing?

On the other hand, they have made a second observation with their implementation where PDN Is tied to VCC_OUT. They’ve monitored/captured the SPI bus communications to the device. The current FPGA control of the CLK and MOSI signals are held low  when not programming/interfacing with the synthesizer. When monitoring the lock signal (out of the synthesizer), it is going low when the CLK signal is pulled low after programming (latch enable remains high). In some reprogramming cases the lock signal recovers almost immediately, in others the lock signal never recovers as seen below.

In  this implementation they have to power cycle to recover the lock signal. They assume if they could toggle the PDN it would recover as well. When implementing a CLK control that keeps it pulled high when not programming/interfacing with the synthesizer, the lock signal remains high (never dropping).

This brings us to the next question since they aren’t sure how the CLK signal should be handled when not programming the synthesizer. The timing waveform on page 11 of datasheet depicts the signal starting low (when performing a SPI write) but the signal description on page 5 mentions this signal has in an internal pull-up when not connected. They say they do seem to maintain a more stable lock signal when the CLK signal is pulled high when not interfacing with the synthesizer.

Any feedback you can provide on the observations is very appreciated.

Hello Patrick,

Thanks for your quick response. 

"can you please clarify which of the scope channels is the 3.3V of the CDCE62005?"

-The Legend for the scope is as follows (my apologies, I forgot to include):

Channel 1: 28V supply into the board
Channel 2: Main 3.3V
Channel 3: 3.3V Supply for Clock Synthesizer

"What is the input reference clock?"

- 10MHz TCXO

"Is this clock already powered and provides stable frequency?"

- The reference CLK and Synthesizer are powered up at the same time. 

"When a crystal is used which model is used?"

- Connor Winfield - M622-010.0M

Sorry I should've clarified but the CLK signal that the latter portion of my most recent response was referring to is the SPI CLK which comes from the FPGA and runs at 5MHz.

Can you comment on what should be done with SPI_CLK signal when the synthesizer is not being programmed?

Thanks so much for looking at this!

-Amanda 

Hello Patrick,

Thanks for your response. How much delay do you suggest on the PDN pin and what do you believe is the range we should maintain for the slew rate (this may be given in the datasheet, I'll check)?

Do you think there is any other way for them to fix what they're seeing without having to use up an FPGA pin (on the PDN pin) as they have been for their current fix? Maybe adding a supervisor so they don't have the stepping and it stays low until it has reached that 2.5V transitional threshold?

-Amanda