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LMX2592 Issues

Genius 5355 points
Other Parts Discussed in Thread: LMX2592

Hi Support,

We have a synthesizer project, the specifications are as following.
1. Reference in: 100MHz OCXO
2. Output frequency range: 7030-7830MHz
3. Spurious: <-50dBc
4. Step size: 1kHz
5. Phase noise -75/-85/-95/-105dBc/Hz @ 100/1k/10k/100kHz frequency offset.

I bought an evaluation board for LMX2592 synthesizer with build-in VCO from Mouser for this project.
After testing, we found that:
1. phase noise can meet specification.
2. There are very high spurious at around -30dBc at frequency of 7.4, 7.6 and 7.8 GHz nearby (Let's say 7.4001GHz).

I check the spurious simulation using PLLatinum simulator tool.
The simulator tool also suggest the same spurious of around -30dBc.

I find out that the spurious is caused by Fvco%Fref and I try to solve the problem by shifting Fref to 150MHz (By doing this, we can solve
the spurious at 7.4 and 7.6GHz nearby, but 7.8GHz spur will remain to be the same).
I created the 150MHz Fref from 100MHz OCXO by /2 then X3 outside the PLL IC.
However, the IC has problem to lock properly with 150MHz reference and PD frequency.
With 3rd order modulator I get a warning and it cannot lock.
With 1st order modulator I can see huge spurious presents.

My question is:
1. Is it possible for this IC to lock to any frequency (fractional mode) properly using 150MHz reference and phase detector frequency?
2. Is there any other solution you can suggest for me to use this IC to meet the requirement of my project?

Thanks.

  • Hi Ikon,

    Since you are running 7.4, 7.6, 7.8GHz, you have 3.7,3.8 and 3.9GHz VCOs, which will have lower N values the higher PFD you go, and thus limit usable MASH orders, as you probably already know. You can try a different combination of your strategy, your current one aims to make the Fvco%Fpd=100.1MHz, try using a combo of OSCin=100M, pre-R=2, mult=4, post-R=3, so you get 100/2*4/3 = 66.6666, then Fvco%Fpd=33.4M. and then you have a N-divider value of 27 so can use any MASH=1,2 or 3. Let me know if that works better.

    regards,

    Brian Wang

  • Dear Brian,

    Please see attached simulation file for PLLatinum Sim.

    According to the simulation, the spur power is -30.911dBc (rename to .sim from .txt).

    Thanks.

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  • Dear Brian,

    Any update?

    Thanks.

  • Hi Ikon,

    I tried this out and get -55dBc spur for 7400.1MHz output and 100MHz input. There are many things that can affect this.

    - reference input signal: is this from a signal generator? in general we notice that higher slew rate helps in IBS spurs. So you see improvements in increasing the amplitude, we also put a limiter to protect the OSCin when we do this, but you can try from -10dBm up to +10dBm to see this. If you have standard LVPECL or LVDS outputs from a clock, those are good too.

    - you are measuring a 100kHz spur, do depending on what you have set for the loop bandwidth, I'm not sure if this is in band or out for you. adjust the charge pump and the spur level will change depending on this setting.

    - then there is moving around the relation of Fvco%Fpd. I tried a 100MHz / 2 * 3 / 7 and get 6 dB improvement. What is your flexibility with Fpd? try a few combinations and see how it helps your use case.