Hi Support,
We have a synthesizer project, the specifications are as following.
1. Reference in: 100MHz OCXO
2. Output frequency range: 7030-7830MHz
3. Spurious: <-50dBc
4. Step size: 1kHz
5. Phase noise -75/-85/-95/-105dBc/Hz @ 100/1k/10k/100kHz frequency offset.
I bought an evaluation board for LMX2592 synthesizer with build-in VCO from Mouser for this project.
After testing, we found that:
1. phase noise can meet specification.
2. There are very high spurious at around -30dBc at frequency of 7.4, 7.6 and 7.8 GHz nearby (Let's say 7.4001GHz).
I check the spurious simulation using PLLatinum simulator tool.
The simulator tool also suggest the same spurious of around -30dBc.
I find out that the spurious is caused by Fvco%Fref and I try to solve the problem by shifting Fref to 150MHz (By doing this, we can solve
the spurious at 7.4 and 7.6GHz nearby, but 7.8GHz spur will remain to be the same).
I created the 150MHz Fref from 100MHz OCXO by /2 then X3 outside the PLL IC.
However, the IC has problem to lock properly with 150MHz reference and PD frequency.
With 3rd order modulator I get a warning and it cannot lock.
With 1st order modulator I can see huge spurious presents.
My question is:
1. Is it possible for this IC to lock to any frequency (fractional mode) properly using 150MHz reference and phase detector frequency?
2. Is there any other solution you can suggest for me to use this IC to meet the requirement of my project?
Thanks.