cdce72010 frequency design

Hello Du,

duuk lee said:

1). I tried to use Webench designer to figure out my frequency design, but failed to get meaningful results.  So I wonder if there is a solution for my design using cdce72010 EVM :

Thanks for trying the Clock Architect tool.  Yes, in your case we need to add the feature to allow you to specify the VCXO frequency to help you with your design.  We will be working to make such an update, for now.

With the 100 MHz reference and the 491.52 MHz VCXO, using an integer PLL will require a phase detector frequency of 160 kHz with M = 625 and Total N = 3072.  Note that the Feedback Divider must be programmed before the PLL N divider and reduce frequency to 250 MHz.  Setting the feedback divider P = 2 will result in 491.52 MHz divided to 245.76 MHz and a PLL N = 1536 will result in PLL lock.  Note, the phase detector frequency is solved by the greatest common divisor of 491.52 MHz and 100 MHz.

The 491.52 MHz clock can be divided by 40 to achieve 12.288 MHz output which is in your required frequency range.

duuk lee said:

2). One additional question is for  M, N dividers - are these dividers can handle divide-by odd-number such as the default  divide-by-125 ?  Also they can divide in step of 1, from 1 to 16384 ? 

Yes, please refer to table 14 on page 55 of datasheet.

73,
Timothy