JESD204B clocking architecture using LMX2592 & LMK04828

Itai Eden1

Intellectual 330 points

Other Parts Discussed in Thread: ADC12J4000, LMX2592, LMK04828

Hello,

In my design I need to supply clocking for a JESD204B interface between the ADC12J4000 and a STRATIX V FPGA.

The FPGS requires other clock signals for additional transceiver interfaces.

Moreover, the design incorporates a DAC (NON-JESD) the I need to provide with a sampling clock as well.

We wish to separate between the clock signals of the ADC & DAC and those of the FPGA. This is in order to keep as clean as possible clocks for the ADC and DAC.

So,

our thought is to use the LMX2592 to produce the sampling clock of 2.7GHz and drive it to 2 separate LMK04828 devices:

- 1 for the DAC & ADC (dev_CLK & SYSREF)

- and 1 for the FPGA (DEV_CLK, SYSREF, and additional clock signals for the transceivers).

Note: I'm using the Fin input of the LMK such that the PLLs are not used in order to allow for a higher frequency

see atached image below:

To my understanding I comply with the JESD clocking requirements:

- DEVCLK & SYSREF of Tx ( ADC) are provided from the same LMK and will be routed together (same trace lengths).

- DEVCLK & SYSREF of Rx (FPGA) are provided from the same LMK and will be routed together (same trace lengths).

- To my understanding it is OK to have a SYSREF to SYSREF delay. this is based on a TI JESD204 presentation & snau139:

* "The only thing that matters for JESD204B is SYSREF to Device Clock timing for the same device. Not SYSREF to SYSREF"

* need for "generating SYSREF for TX and RX at the same time (or with a constant delay) using a single clock source" [snau139 slide 6] see attached image below:

My questions are:

1. is this an adequate solution?

2. Are there any cons compared with the solution that is used in the ADC12J4000 EVM where the ADC DEVCLK is driven from a synthesizer and the ADC SYSREF, FPGA SYSREF & FPGA DEVCLK from the LMK?

3. Are there any issues that I should be concerned about when implementing such a solution?

4. will it make the setup more complicated (will it need additional delay settings in the LMK to make it work for example)?

Best regards,

Itai

over 9 years ago

0 Timothy T over 9 years ago

TI__Mastermind 28590 points

Itai Eden1 said:
1. is this an adequate solution?

I think this can work well. For high frequency Fin, a simple 100 ohms is not good as the LMK0482x input impedance is low at 2.7 GHz. I've traditionally used a 3 dB resistive pad, although at high frequency I'm considering in the future looking into some other methods of matching.

Since you show SYSREF from both LMK0482x, you need to align them/SYNC them somehow. One way may be treat one of the devices, as the master and then drive a SYSREF into the CLKin0 of the other to SYNC it's SYSREF divider... or to just distribute directly. Note, right now we don't have the setup and hold windows defined for CLKin0 (SYSREF) to CLKin1 (Device Clock) SYSREF distribution.

Itai Eden1 said:
2. Are there any cons compared with the solution that is used in the ADC12J4000 EVM where the ADC DEVCLK is driven from a synthesizer and the ADC SYSREF, FPGA SYSREF & FPGA DEVCLK from the LMK?

The EVM approach can introduce some issue with PVT variation and placement of SYSREF in device clcok. By using the same device, this tends to minimize that skew variation. The ADC12J4000 does have controls to allow you finely adjust the valid SYSREF window.

Itai Eden1 said:
3. Are there any issues that I should be concerned about when implementing such a solution?

You are referring to the ADC12J4000 EVM approach? Primarily the skew variation.

Itai Eden1 said:
4. will it make the setup more complicated (will it need additional delay settings in the LMK to make it work for example)?

You may be able to do some of the SYSREF delay variation compensation on the ADC12J4000.

73,
Timothy

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JESD204B clocking architecture using LMX2592 & LMK04828