LMK03328 input clock jitter specification

F.N

Other Parts Discussed in Thread: LMK03328

Hi team,

My customer is going to use LMK03328 with an external clock input as reference clock.

So the customer wants to know the external clock input jitter specification to realize
the output jitter characteristics which is described in the datasheet page.17
"8.26 Closed Loop Output Jitter Characteristics" section.

Please let me know it.

Best regards,
Fumio Nakano

over 9 years ago

0 Alan O over 9 years ago

TI__Mastermind 32575 points

Hello,

The jitter specs in the datasheet are based on the test condition using the on-chip oscillator circuit with XTAL input. The internal XO source (after buffering directly to the output, bypassing the PLL) shows less than ~80 fs rms jitter, typ (12 kHz - 20 MHz) with 50 MHz XTAL input. To achieve the specified performance, they should use an external oscillator with similar jitter (80~100 fs rms). Note the PLL can attenuate some high frequency noise, like above ~1 MHz.

In WEBENCH Clock Architect, the customer can enter a phase noise model for their external reference clock, design the PLL loop filter, and simulate the final output clock jitter and see the input clock noise contribution.

Alan

0 F.N over 9 years ago in reply to Alan O

TI__Expert 8760 points

Alan-san,

Thank you for your quick reply.

Your reply was very helpful.
Thank you !!!

Best regards,
Fumio Nakano

Clock & timing

Clock & timing forum

LMK03328 input clock jitter specification