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LMK04828 0-delay mode

min hu
Intellectual 990 points


o-delay mdoe,N divider = 4,since N divider are always phase aligned with reference input,divider path delay is same between chips.

with the same reference input and integer N number, VCO phase of difference chips should be aligned?

device clock are multiple of SYSREF and sync with SYSREF,  so device clock phase of difference chips should also be aligned?

  • Intellectual 990 points
    why must set N = 1,in multiple board synchronization？
  • TI__Mastermind 28560 points

    It is acceptable for N = 4 and keep determinism of SYSREF between both systems.  It simply means that the SYSREF frequency is 38.4 MHz = 4 * 9.6 MHz.

    What's critical is that there is no effective division in the forward path.  Since R = /1, there is no division.  What I mean by that, is if R=/2 and N=/8 the fraction of N/R reduces from 8/2 to 4/1.  Which means there is only frequency multiplication happening from the reference to the SYSREF frequency.  So you are correct that this would be aligned.

    Again device clock is also aligned because it is just a multiplication.  If for example R = /3 and N = /4.  Then you'd end up with 3 possible phase relationships in 0-delay mode... thereby no longer achieve deterministic phase.


    73,
    Timothy