CDCM6208 / reference clock for SRIO SW

Toshiyuki

Other Parts Discussed in Thread: CDCM6208

Hello,

We are considering clock generator(Input:50MHz, Output:156.25MHz) for SRIO SW. The SRIO SW require the jitter specs as follows.

RJ(12kHz-20MHz)=1ps rms(Max), RJ(2MHz-20MHz)=0.8ps rms(MAX)

DJ(750kHz-10MHz)=1.1ps pp(MAX),DJ(200KHz-50MHz)=2.2ps pp(MAX)

Please let me know whether CDCM6208 could meet the specs.

Best Regards,

Toshiyuki

over 9 years ago

0 Toshiyuki over 9 years ago

Mastermind 7075 points

Your immediate response is highly appreciated.

0 Julian Hagedorn over 9 years ago in reply to Toshiyuki

TI__Mastermind 20900 points

as per email:
Yes, you can recommend CDCM6208 device. As the Frequency multiplication ratio is integer only, the
device performance for both DJ & RJ is better than the specs you have mentioned for the SRIO SW.
Attached are the snapshots of Random jitter simulation for your reference.

Julian

0 Toshiyuki over 9 years ago in reply to Julian Hagedorn

Mastermind 7075 points

Hello Julian - san,

Thank you for your reply. In customer's case, 156.25MHz are for SRIO, and 122.88MHz is for the other device. We are considering that CDCM6208 make three 156.25MHz outputs and one 122.88MHz output. What is the value of DJ for 156.25MHz ?

Best Regards,

Toshiyuki

0 Puneet Sareen over 9 years ago in reply to Toshiyuki

TI__Expert 8865 points

Hello Toshiyuki-san

For 156.25MHz, the DJ<1ps. What are the requirements for 122.88MHz? For this, fractional channel has to be used from CDCM6208 device.

Regards
Puneet

0 Toshiyuki over 9 years ago in reply to Puneet Sareen

Mastermind 7075 points

Hello Puneet - san,

It was my typo. I'm sorry for confusing you. 125MHz is required for FPGA.

wrong:122.88MHz

correct:125MHz

Best Regards,

Toshiyuki

Clock & timing

Clock & timing forum

CDCM6208 / reference clock for SRIO SW