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LMK04826 on ADS52J90EVM...

Amanda Ross95
Intellectual 2740 points
Other Parts Discussed in Thread: ADS52J90, LMK04826, LMK04821

Hello,

Originally I was typing this out on the Medical Hi-Rel forum because it involves the ADS52J90 but the more I typed, the more I realized this might be a question for you guys so here goes, let me know if it needs to be moved.. 

I have a customer who would like to check the compatibility of the JESD204b output from the ADS52J90 with their system. 

The default scripts that come with this EVM only configure the LMK04286 device as simply a clock distribution device and relies on the user to provide an external clock via the SMA. So the onboard oscillators are not used.

The customer is running the JESD204b stream at 3.0Gbs and they need to provide the ADS52J90 with a 3Gbs/40 = 75MHz clock. So they're looking to generate that 75MHz clock using the onboard 100MHz clock oscillator paired with the LMK device. Is there anyway you could provide the required register settings to be able to do this?

He intends to edit the .cfg file that comes with the EVM, just to use that GUI. So he mostly needs the hex file register settings so he can manually edit the appropriate .cfg file (two hex files, one that outputs 75MHz and another which outputs 50MHz). 

Please let me know if you nee dmore information or if there is something I am missing?

-Amanda

  • 0
    TI__Mastermind 28560 points

    Hello Amanda, since this is related to the EVM software of the ADS52J90, you'll need to move it to the other form... unless this can help you, and actually some of my input about the frequency issue may be of importance when you re-post.

    To get 75 MHz out from LMK04826, you'll need to program the device to use VCO0 with a VCO frequency of 1950 MHz with a /26 to get 75 MHz.  To lock the PLL you'll need to divide the 100 MHz reference to 50 MHz to allow the PLL_N = 13 and PLL2_P = 3 (total N = 36).

    Attached is a TICS Pro configuration file and a .txt file containing the registers needing to be programmed to achieve 75 MHz output on DCLKout2.  I also setup for pulser mode with 10 MHz SYSREF on SDCLKout3.  However from the LMK side, that doesn't have to be used and won't toggle (because it's in pulser mode) unless the SYSREF is explicitly requested.  I also assumed that it EVM uses DCLKout2 to drive the sample clock.  If need be you can load the .TCS file and change the outputs and re-export the hex register file.

     Beyond this, the ADC team will be able to help you with a configuration for their software.

    73,

    Timothy


    LMK04826 TICS config for 75 MHz.tcs 

    Fullscreen HexRegisterValues_75MHz_DCLKout2.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x01001A
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x0106F9
R263	0x010755
R264	0x01081A
R265	0x010955
R266	0x010A55
R267	0x010B00
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F55
R272	0x011008
R273	0x011155
R274	0x011255
R275	0x011300
R276	0x011402
R277	0x011500
R278	0x0116F9
R279	0x011700
R280	0x011818
R281	0x011955
R282	0x011A55
R283	0x011B00
R284	0x011C02
R285	0x011D00
R286	0x011EF9
R287	0x011F33
R288	0x012008
R289	0x012155
R290	0x012255
R291	0x012300
R292	0x012402
R293	0x012500
R294	0x0126F9
R295	0x012700
R296	0x012808
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012EF9
R303	0x012F00
R304	0x013006
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013402
R309	0x013500
R310	0x0136F9
R311	0x013733
R312	0x013800
R313	0x013902
R314	0x013A00
R315	0x013BC3
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x014008
R321	0x014100
R322	0x014200
R323	0x014313
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015664
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A64
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016102
R354	0x016264
R355	0x016300
R356	0x016400
R357	0x01650A
R369	0x0171AA
R370	0x017202
R380	0x017C18
R381	0x017D77
R358	0x016600
R359	0x016700
R360	0x01680D
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

  • 0 in reply to Timothy T
    TI__Intellectual 2740 points

    Thank you so much for your quick response. I believe this is exactly what he is asking for. Can you detail also what to put in to get 50MHz out?

  • 0 in reply to Amanda Ross95
    TI__Mastermind 28560 points
    Hello Amanda,

    Unfortunately 50 MHz is below the capabilities of LMK04826 for a device clock, with VCO0 tuning as low as 1840 MHz, and the max clock output divide of 32, you'll get 57.5 MHz. The SYSREF divider will easily get them to 50 MHz, but that can't be routed to a device clock - so I think it will be problematic for them - not to mention they may still want to be using that SYSREF divider.

    What they need is to use the LMK04821. This has a VCO divider programmable from 2 to 8 on the VCO1 output. This allows the user to achieve the lower frequencies. For example with VCO = 3000 MHz and VCO_DIV = 2, the CLKout_DIV = 30 results in 50 MHz at output. This will result in better performance because VCO1 has better performance that VCO0 of this product family and because the phase detector frequency = 100 MHz, the PLL noise will be improved.

    73,
    Timothy
  • 0 in reply to Timothy T
    TI__Intellectual 2740 points
    Could we obtain the register settings for the 57.5MHz output instead? This will still work since the whole idea is for them to also test at a lower target rate than the 75MHz and see how it compares.

    I downloaded TICS and understand how you're exporting but I'm using it pretty blindly and I don't want to provide the wrong information.
  • 0 in reply to Amanda Ross95
    TI__Mastermind 28560 points

    Since you're using a 100 MHz VCXO, achieving the lowest VCO frequency for 1840 MHz requires me to reduce the phase detector to 20 MHz.  To keep the PLL operating as close as possible for apples-to-apples comparison, I'm providing you a config which provides 59.375 MHz.  This is achieved by dividing 1900 MHz by 32.  For the PLL2 to lock to 1900 MHz, the PLL2_N = 19 and th PLL2_P = 2; for a total N divider of 38.  38*50 MHz = 1900 MHz.

    LMK04826 TICS config for 59.375 MHz.tcs

    Fullscreen HexRegisterValues_59.375MHz_DCLKout2.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x01001A
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x0106F9
R263	0x010755
R264	0x010800
R265	0x010955
R266	0x010A55
R267	0x010B00
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F55
R272	0x011008
R273	0x011155
R274	0x011255
R275	0x011300
R276	0x011402
R277	0x011500
R278	0x0116F9
R279	0x011700
R280	0x011818
R281	0x011955
R282	0x011A55
R283	0x011B00
R284	0x011C02
R285	0x011D00
R286	0x011EF9
R287	0x011F33
R288	0x012008
R289	0x012155
R290	0x012255
R291	0x012300
R292	0x012402
R293	0x012500
R294	0x0126F9
R295	0x012700
R296	0x012808
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012EF9
R303	0x012F00
R304	0x013006
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013402
R309	0x013500
R310	0x0136F9
R311	0x013733
R312	0x013800
R313	0x013902
R314	0x013A00
R315	0x013BBE
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x014008
R321	0x014100
R322	0x014200
R323	0x014313
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015664
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A64
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016102
R354	0x016224
R355	0x016300
R356	0x016400
R357	0x01650A
R369	0x0171AA
R370	0x017202
R380	0x017C18
R381	0x017D77
R358	0x016600
R359	0x016700
R360	0x016813
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

  • 0 in reply to Timothy T
    TI__Intellectual 2740 points

    Sorry to keep at this but if we could provide VCXO with 10MHz or 40MHz, then we would be able to synthesize from there to the necessary 50MHz out, correct? What register settings would we use to do that?

    Thanks for your patience with all this.