Problems about using LMK04828 's HOLDOVER MODE. How to write the 0x14D,0x14E and 0x150

Zhipeng lv

Other Parts Discussed in Thread: LMK04828, DAC38J84

Hi ! Recently I use the LMK04828 to provide the clock signal for DAC38J84. There are some problems about using LMK04828's HOLDOVER MODE.

1.What's the meaning of the DAC_TRIP_LOW / DAC_TRIP_HIGH in register 0x14D and 0x14E. Could you please give me more detail information about the DAC Trip Value? How do I write 0x14D and 0x14E to use the HOLDOVER MODE.

2.How do I write the register 0x150 to enable the HOLDOVER MODE. HOLDOVER_PLL1_DET = 1, HOLDOVER_LOS_DET =1, HOLDOVER_HITLESS_SWITCH =1, HOLDOVER_EN =1 ,right?

What's the meaning of the HOLDOVER_VTUEN_DET in register 0x150. Whether HOLDOVER_VTUNE_DET must be set to 1 to enable the HOLDOVER MODE?

3. I refer to the DAC38J84 evaluation to design the schematic diagram of LMK04828. The CVHD-950-122.88 is a single end output VCXO. I find the output pin of the CVHD-950-122.88 is connected to the Oscin_n pin of LMK04828. The Oscin_p pin is connected to the ground.

However, according to my view, the output pin (pin 4 in the six footprint package)of the CVHD-950-122.88 should be connected to the Oscin_p and the Oscin_n should be connected to the ground . I want to consult the reason of the design in the DAC38j84 evaluation. Whether the output pin of the CVHD-950-122.88 must be connected to the Oscin_n pin.

over 8 years ago

0 Julian Hagedorn over 8 years ago

TI__Mastermind 20900 points

Hello Zhipeng,

1. these values can be used for enter holdover through monitoring the tuning voltage of the VCXO. DAC_TRIP_LOW/HIGH set upper/lower limit that defines a valid control voltage. In case the control voltage of the VCXO crosses one of these limits the device enters holdover.

2. most important is HOLDOVER_EN =1 to enable Holdover. HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_HITLESS_SWITCH are options for entry/exit.
- Entry:
-> HOLDOVER_PLL1_DET = if PLL1 loses lock;
-> HOLDOVER_LOS_DET = if a loss of signal (reference clock) is detected (LOS needs to be enabled);
-> HOLDOVER_VTUNE_DET = enables the rail detection and uses DAC_TRIP_LOW/HIGH as limits.
- Exit:
-> HOLDOVER_HITLESS_SWITCH = waits until VCXO and reference clock phases are aligned before enabling the charge pump again for locking.
- TRACK_EN = tracks vtune and sets control voltage to the last known state in holdover
- MAN_DAC_EN = forces a predefined control voltage (MAN_DAC) when in holdover

so, it depends on what is the trigger signal to activate holdover. In case the time is known when to enter/exit holdover HOLDOVER_FORCE could be used as well

3. the single ended clock can be connected to both OSCIN_P or OSCIN_N. On our EVM the OSCIN_N pin was used to avoid crossing of PCB traces as we do have the option to place a differential VCXO as well.

regards,
Julian

0 Zhipeng lv over 8 years ago in reply to Julian Hagedorn

Intellectual 465 points

Hello Julian,

Thank you for your reply. But there are also two points without understanding for me.

1. HODLOVER_HITLESS_SWITCH: What's the difference between Hard Switch and Hitless switching? Which is better for Holdover Mode?

2. HOLDOVER_FORCE: HOLDOVER_FORCE =1 means the LMK04828 must entry HOLDOVER MODE. Can I understand HOLDOVER_FORCE like this?

regards,
Zhipeng

0 Julian Hagedorn over 8 years ago in reply to Zhipeng lv

TI__Mastermind 20900 points

Hello Zhipeng,

1. with HOLDOVER_HITLESS_SWITCH the device waits until the phases of PLL1_RDIV and PLL1_NDIV outputs are aligned. That means the PLL locking process will be smoother. In case there is only a small ppm error between reference clock and PLL1 feedback, the time until holdover exits could be longer. This can be solved by using MAN_DAC by increasing the ppm error. Without HOLDOVER_HITLESS_SWITCH the locking process can result in a bigger frequency change depending on the bandwidth.
2. HOLDOVER_FORCE forces the device into holdover. Meaning as soon as you set the bit to '1', the device enters holdover (depending on whether you have MAN_DAC_EN or TRACK_EN set, the behavior is different, see previous post).

regards,
Julian