LMK61E2 Phase Noise: Integer Mode vs Non-Integer Mode

Samuel Jaffe

Hi E2E,

My customer is looking to get a 192MHz clock with low phase noise at 1kHz and 10kHz. The datasheet says integer mode will improve phase noise over non-integer mode but the Webench simulations show no difference. The sim reports -133.8dBc/Hz but the customer would like to see better performance. The datasheet suggests that it can do better than -133.8dBc/Hz. The customer is using the 'auto' loop-filter for both.

1. Should the customer switch to integer mode?

2. What sort of improvement can we expect from this change?

3. Is there any way to get the performance up?

Thanks,

-Sam

over 9 years ago

0 Timothy T over 9 years ago

TI__Mastermind 28590 points

Hello,

You should already be in integer mode. Notice in the lower right of the sim screen below the phase noise plot you should see PLL N = 48 + 0/1. This suggests integer mode.

Also notice that the noise profile impacting your performance is the VCO, not the PLL. So by designing a wider loop bandwidth, we can improve the 1 kHz to 10 kHz noise as the loop filter presents a high pass filter to the VCO.

To increase the loop bandwidth, click Loop Filter tab. Change charge pump gain from 1.6 mA to 6.4 mA. Click the oranged "Choose RC Components for me." You will get a warning about components limiting the filter, but your result will be a 784 kHz, 87 degree filter. Changing back to the Outputs tab you will find the VCO noise has been attenuated and improved. You can also see the VCO noise has been attenuated to about the level of the PLL at it's peak

For 192 MHz:

Offset	Before (1.6 mA CP)	After (6.4 mA CP)
1 kHz	-132.9 dBc/Hz	-135.1 dBc/Hz
10 kHz	-133.8 dBc/Hz	-141.2 dBc/Hz

73,
Timothy

0 Samuel Jaffe over 9 years ago in reply to Timothy T

TI__Mastermind 25590 points

Timothy,

Thank you for your detailed reply. It worked!

-Sam

Clock & timing

Clock & timing forum

LMK61E2 Phase Noise: Integer Mode vs Non-Integer Mode