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LMK04828: LMK04828 timing relationship when switching from SYSREF pulse mode to SYSREF continuous mode

Yarn Guo
Intellectual 1440 points
Part Number: LMK04828
Other Parts Discussed in Thread: TICSPRO-SW, CODELOADER

Hi, Team:

We happened to a  phase alignment issue when switching from SYSREF continuous mode to SYSREF pulse mode. SYSREF frequency is 7.68MHz and Device clock frequency is 122.88MHz.

-        First, we set SYNC_MODE = 1 (sync event from SYNC pin), SYSREF_MUX = 1 (normal SYNC), then toggle the SYNC_POL to perform a SYNC event to get all SYSREF and device clock synchronized.

-        Second, Set SYSREF_MUX to 3 to output continuous SYSREF. And also tune the local Digital DLY of SYSREF to make the SYSREF rising edge delayed Device clock rising edge by 2.5nS.

-        Then, We set SYNC_MODE = 3(SYNC event from SPI write), SYSREF_MUX = 2 (SYSREF pulser). When we program SYSREF_PULSE_CNT, we can get the desired # of SYSREF pulses, but the phase alignment relationship between SYSREF and device clock has been changed from 2.5nS to 300ps.

Do you think that timing relationship between SYSREF and device clock can be changed when switching from SYSREF continuous mode to SYSREF pulse mode?

Really appreciate your great help!

Thank you

Yarn

  • 0
    TI__Mastermind 28550 points

    When performing the first SYNC, all the SYNC_DIS#/SYNC_DISSYSREF bits = 0.  After his, change = 1.  Could you be accidentally syncing the clocks again with SYSREF?

    Also, be aware that the ticspro-sw (TICS Pro) supports LMK04828 profile which is improved over the CodeLoader LMK04828 profile.

    73,
    Timothy

  • 0 in reply to Timothy T
    TI__Intellectual 1440 points

    Hi, Timothy:

    Thank you for your prompt help. I can verify this on EVM and the phase doesn't moving with propoer register writes.

    Thank you!

    Yarn

  • 0 in reply to Yarn Guo
    TI__Mastermind 28550 points

    Ok great.  My understanding is that after adding the SYNC disable bit programming, everything is working.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 10 points

    Hi , now I am debugging the LMK04828, and the DCLKout2(Device clock,LVPECL) outputs correct signal(245MHz), and the SDCLKout2(SYSREF,LVDS) pin have no signal, according to the divider setting ,  the pin should output 24.5MHz signal, and what's the reason?

    I generate the sync pulse using SPI(toggle SYNC_POL bit),  after that I set the SYNC_DIS2 and SYNC_DISSYSREF bit.

  • 0 in reply to junling meng
    TI__Mastermind 28550 points
    Can you share your full programming with me?

    Here are some bits to check for SYSREF output:

    On SYNC/SYSREF tab:
    SYSREF_PD = 0
    SYSREF_CLR = 0
    SDCLKout3_DIS_MODE = 0 (Active) [now SYSREF_GBL_PD bit has no effect]

    On clock outputs:
    SDCLKout3_MUX selects SYSREF.
    SDCLKout3_PD = 0
    And naturally the SDCLKout3_FMT selecting a valid output clock. Note if using LVPECL or LCPECL, a valid termination must be placed to get clocks out. A common termination is to place emitter resistors.

    73,
    Timothy