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LMK04828: Using LMK04828 in cascaded 0-delay mode (only use PLL2)

Part Number: LMK04828
Other Parts Discussed in Thread: CODELOADER, TICSPRO-SW

Hi,

I'm using LMK04828 in cascaded 0-delay mode, and only  PLL2 is used, PLL1 is powerdown.

Input 100MHz reference clock at OSCIN, channel 0 and 1 output is 100MHz, other channels are 500MHz.

If i disable 0-delay mode, LMK04828 can lock normally, which i can check from the lock output pin;

but if I enable 0-delay mode, the lock output pin is always switching between 0 and 1.

i have attached the SCH, codeloader setting and registers.

Please help to check it, and help on it.

Thanks .

WandaLMK04828 codeloader.docx

R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R256	0x010019
R257	0x010155
R259	0x010300
R260	0x010402
R261	0x010500
R262	0x010680
R263	0x010711
R264	0x010805
R265	0x010955
R267	0x010B00
R268	0x010C02
R269	0x010D00
R270	0x010E80
R271	0x010F11
R272	0x011005
R273	0x011155
R275	0x011300
R276	0x011402
R277	0x011500
R278	0x011680
R279	0x011711
R280	0x011805
R281	0x011955
R283	0x011B04
R284	0x011C02
R285	0x011D00
R286	0x011E80
R287	0x011F11
R288	0x012005
R289	0x012155
R291	0x012300
R292	0x012402
R293	0x012500
R294	0x012680
R295	0x012711
R296	0x012805
R297	0x012955
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012E80
R303	0x012F11
R304	0x013005
R305	0x013155
R307	0x013300
R308	0x013402
R309	0x013500
R310	0x013680
R311	0x013711
R312	0x01381E
R313	0x013900
R314	0x013A00
R315	0x013BC8
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F15
R320	0x01408F
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x014480
R325	0x01457F
R326	0x014600
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015664
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A64
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016102
R354	0x0162A5
R355	0x016300
R356	0x016400
R357	0x01650C
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x016805
R361	0x01695D
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
LMK04828 SCH.pdf

  • Hello Wanda,

    Please try downloading the ticspro-sw, this software is much more user friendly for 0-delay mode.  We're also continuing to upgrade the LMK0482x to make it easier to use in the TICS Pro software.

    For the PLL2 to lock in 0-delay, Select PLL2 NCLK MUX = FB Mux, set FB_MUX_EN = 1,

    To have 0-delay to 100 MHz, DCLKout6, DCLKout8, or SYSREF must be set to 100 MHz; or you could feed-back the 100 MHz to CLKin1 port and use External Feeback.  Note, when using DCLKout6 or 8.  The clock output driver doesn't actually have to be active, it can be powered down.   Just the divider must be powered up by setting CLKout6_7_PD = 0 or CLKout8_9_PD = 0.

    Set PLL2 N = 1 given your example of 100 MHz input and 100 MHz clock being fed back, however the PLL2 N Cal divider for PLL2 0-delay must be set to lock to VCO frequency given selected PLL2 N Prescaler.  Suppose your VCO is 3000 MHz and PLL2_P = 2; then this should be 15.

    Hope this helps!

    73,
    Timothy.

  • I just saw that your ADCLK is on CLKout6 and CLKout8. If this is not 100 MHz, you'll need to use SYSREF divider (or external feedback; which appears may be too late.

    To have determinism, you'll also need to SYNC all the dividers together.
  • Hi Timothy,

    This is the codeloader setting file i finally used.

    Would you please help to check it, if anything need change, please help to generate one new version.

    Thanks.

    Wanda

    100M_S.zip

  • Timothy,
    I have download TICS Pro, would you please hlep to use TICS Pro to generate the setting which i need.
    This is new to me, thank you very much.
    Also as my last reply, please also help to check the Codeloader setting.

    Thanks.
    Wanda
  • Closed off-line.