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LMK04828: LMK04828

adomino
Intellectual 1000 points
Part Number: LMK04828
Other Parts Discussed in Thread: LMK04821

Hello, I have a few questions on how LMK04828 behaves on first power –up, before it is initialized.  

  1.  Before programming anything, what is the operational state of Clock Group lines?

  2.  LMK04828 CS* (pin 18) is CMOS.  Does that pin have built-in pull-up or pull-down?  If so, what is the nominal resistance value?

  3.  While CS* is logic High, what is the operational status of the internal PLL(s) and Clock Group output lines?

  • 0
    TI__Mastermind 28550 points

    Hello,

    adomino said:
      1.  Before programming anything, what is the operational state of Clock Group lines?

    These are the clock outputs you are referring to?  Table 22 shows the POR formats of the DCLKout and SDCLKout.  LMK04821 has all CLKouts powered down, LMK04828 has DCLKout4,6,8,10 as LVDS.  Table 16 shows the default DCLKoutX_DIV values, /8 for the enabled outputs.  This /8 frequency is specified in the electrical specs on page 19 as fCLKout-startup and is ~315 MHz for LMK04828, but can experience a glitch during calibration to final frequency.

    Table 23 (register 0x138) shows OSCout default as LVPECL 1600 mVpp and the same frequency as VCXO input.  We find this to be the most useful start-up clock since there is no glitch and even with a VCXO, it's very close to final frequency at start-up.

    adomino said:
      2.  LMK04828 CS* (pin 18) is CMOS.  Does that pin have built-in pull-up or pull-down?  If so, what is the nominal resistance value?


    The electrical specs for SCK, SDIO, CS* on page 22 show they are high impedance with a max of +/- 5 uA.

    adomino said:
      3.  While CS* is logic High, what is the operational status of the internal PLL(s) and Clock Group output lines?


    In general, CS* has no impact on the operational status.

    73,
    Timothy