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LMK04803: SYNC

new2day
Expert 1950 points
Part Number: LMK04803
Other Parts Discussed in Thread: CODELOADER,

The outputs from two of this PLL won't aligned, in our case,

1. the clock to these two PLL are algined (in SYNC)

2. the SYNC signals to both PLL are aligned (in SYNC)

3. SYNC are enabled on all outputs of them

4. DDLY at their default

5. both PLL mode x"6"

Expect to see all outputs are aligned after toggling the SYNC as stated in the datasheet. Thanks.

  • 0
    TI__Mastermind 28560 points

    One way to consider synchronizing the outputs is to use 0-delay.  The SYNC then will locally SYNC the dividers, and because the phases are the reference are aligned, the phases of the clock outputs will be aligned/deterministic based on the feedback clock.

    See the LMK04803 eval board instructions for more details on programming 0-delay mode with CodeLoader.  When using a low frequency reference such as 10 MHz however, using a 10 MHz feedback clock may cause your jitter to increase, you could sim to determine if this is acceptable for your application.

    -

    As for issuing a SYNC signal, this can be used to align the clock outputs.  However the SYNC path is not a high speed path and there could be some variation.  For testing one part at one temp, unless some meta-stable condition is achieved, you should be able to provide the SYNC and see the clocks operate deterministically in phase.
       - After toggling SYNC, are the phases close?

       - How are you distributing / toggling SYNC?  Are you able to hold the clock outputs in reset?

       - Is this using EVMs or a final or proto board?

       - Can you tell me more about your application?  Input and output frequencies?

  • 0 in reply to Timothy T
    Expert 1950 points

    1. The phases between two of this PLLs are not aligned nor closer.

    2. the SYNC signal is sending from the master board to the slave board so that the SYNC signals are the same on both! 

    3. the clock outputs can be hold when SYNC signal is LOW (active)

    3. Our boards is used.

    4. Our application is data acquisition.

    5. The input is 10MHz or 100MHz that 100MHz was used for the testing so far. 

    6. the output clock are programmable. from 100MHz or 250MHz to 1000MHz (1GHz).

    7. right now, only PLL2 is used! (no feedback) The DDLYs are all set to value of '0' (5 clock cycles) with Analog delay powered down!

    8. The internal VCO is set to 2000MHz (2GHz).

  • 0 in reply to new2day
    Expert 1950 points

    Just revisit this one, thank you.

    1. any updates?

    2. are you suggesting that by toggling SYNC pin won't make multiple of this PLL in SYNC even if the REF Clock are aligned to all OSCin of the PLLs?