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LMK03318: About CodeLoader setting (LMK03318)

Satoshi
Guru 19645 points
Part Number: LMK03318
Other Parts Discussed in Thread: CODELOADER

Please let me know about unclear points below of CodeLoader.

-------------------------------------

①Output setting

　If the case of LVDS output, which correct HCSL setting for n-ch?

　Is "CMOS(Hi-Z) correct?

②PRI/SEC REF input

　Which is recommend for Max Gain or Min Gain?

　Is there way to distinguish Max Gain or Min Gain depending on?

③LF type of PLL setting

　I think that 3rd order LF is LPF, is it correct?

④PLL setting

　Please let me know about mean of Dither and Stretch.

　Is there configure case for other than "Suggested PLL Setting"?

-------------------------------------

Best regards,

Satoshi

  • 0
    TI__Expert 4415 points

    Hi Satoshi,

    1. In case of LVDS setting, n-ch setting does not matter. It is fine to set it to CMOS(Hi-Z).

    2. Max gain is always recommended for best signal integrity. There isn't a way to distinguish the setting.

    3. Yes, the PLL loop filter is a low pass filter.

    4. See the below sections (taken from the datasheet) for a description of Dither and Stretch.

    For Stretch, the suggested PLL setting is best (200ps for Integer-N mode and 600ps for Fractional-N mode).

    Enabling dithering can reduce sub-fractional spurs in fractional-N mode, but usually at a tradeoff for some phase noise. When in Frac-N mode with equivalent denominator > 200 and divisible by 2 or 3, a dithering setting of 'Weak' usually is the best balance between spur reduction and phase noise increase.

    Regards,

    -Tim