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LMK04821: Single Loop Example

Part Number: LMK04821


Hello,

Is there an example of the LMK04821 being used in single loop configuration?  Datasheet mentions when simulating single loop solutions, set PLL1 loop filter block to "0 Hz LBW" and use VCXO as the reference block, but not much details.

Thanks,

Chuchen

  • Hello Chuchen,

    What sort of example are you looking for? Fundamentally it's normal operation with PLL1 powered down.

    73,
    Timothy
  • Hi Tim,

    The customer would like to see a schematic example.  They are wondering if there's any changes needed on the input/output.

    Thanks,

    Chuchen

  • Hello,

    There are no changes to the schematic, we still require all pins to be powered. The CLKin pins can be left NC.

    The OSCin will be connected appropriately per input clock source type, depending on if it is single ended (like LVCMOS or sine wave) or differential LVCMOS (like LVDS or LVPECL). Please refer to section 10.2.2 of the datasheet about how to connect the input. I just have noted that this section refers to CLKin and OSCin, but then only talks about CLKin in the text. Basically everything applies to OSCin, except that for OSCin, when operating single ended care must be taken to be below the maximum Vpp signal. For a 3.3 V CMOS signal, this can be done with a voltage divider as shown in the EVM schematic. Note that CLKin has a MOS input mode which can accept DC coupled 3.3 V signals.

    73,
    Timothy