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LMK04828: LMK04828 Holdover modes

sergey bartsevich
Prodigy 130 points

Part Number: LMK04828

Hi!

I have a custom board with LMK04828 in dual loop mode, it works fine until it comes to managing erroneous conditions on reference clock input (CLKin_0 in my case). I need the device to enter holdover (either fixed MAN_DAC or last tracked "good" point, doesn't matter now) both on "no signal on reference input" and on "reference frequency out of VCXO tuning range for PLL1 lock". I'm able to enter holdover only in conditions when:

1) HOLDOVER_EN & HOLDOVER_PLL1_DET are set and NO other holdover conditions are enabled;

2) MAN_DAC_EN and/or TRACK_EN are set;

3) reference signal lost from locked condition (i.e. when it was in range prior to being switched off).

The device DOES NOT enter holdover when reference clock goes too much low/high on frequency and PLL1 looses lock and when reference switching off in these conditions.

I have tried different modes with no success. If HOLDOVER_VTUNE_DET is enabled, the device does not enter holdover in any conditions, with different DAC trip settings and so on. Moreover, when VTUNE_DET is disabled, the device outputs DAC trip conditions correctly through CLKin_SEL0 pin, but if i turn VTUNE_DET ON, it stops doing so.

So, the main question is: how should i set up holdover settings for LMK04828 to enter holdover when the reference signal frequency goes out of range?

Thanks in advance,

Sergey

  • 0
    Prodigy 130 points
    Findings so far: the device is unable to enter holdover if HITLESS_SWITCH is disabled. If it is enabled, device successfully enters holdover both on PLL1 DLD loss and VTUNE_DETECT. But it never exits if it entered on VTUNE_DETECT condition.
  • 0 in reply to sergey bartsevich
    TI__Mastermind 28590 points
    Hello Sergey,

    Sorry for the delay in response. Yes, the HITLESS_SWITCH must = 1 for automatic holdover operations. Otherwise it allows the PLL to re-lock. The benefit of this is when using the pin control mode, if holdover is set by pins, and you want to exit holdover immediately, use HITLESS_SWITCH = 0. Otherwise, you will change the pin control from holdover mode to CLKinX and it will wait for the PLL phases to align before exiting holdover which may take some time.

    As for not exiting if VTUNE_DETECT triggered holdover. Side note, we recommend VTUNE_DETECT mode only when using the manual DAC setting for holdover voltage.
    - If you increase the PLL1_DLD_CNT value, does that help you exit holdover? There could be a case where you bounce between locked and holdover states if the PLL1 isn't given a long enough time to settle. For example, holdover is engaged with forced Vtune. Then it exists because signal meets PPM requirements, signal starts to lock but has not fully settled, it may go out of the lock phase window triggering holdover again. Cycle can repeat.

    73,
    Timothy
  • 0 in reply to Timothy T
    Prodigy 130 points
    Hello Timothy,
    Thank you for the reply. Got the idea of how it is intended to work. Unfortunately, playing with DLD counter and other locking-related parameters did not help, once entered holdover on VTUNE_DETECT it never exits automatically. It is not necessary in my current design, just wanted to use all capabilities available.

    Sergey