• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 777 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828: LMK04828

Randy Draper
Prodigy 65 points

Part Number: LMK04828
Other Parts Discussed in Thread: DAC38RF83, , LMK04808

Sirs:

I am trying to connect the LMK04828B to the DAC38RF83 and a Lattice ECP5-5G FPGA and I am using the PDF document tidrpe0.pdf from Texas Instruments as a reference design.

On page 5 of the tidrpe0.pdf document, pins 34 and 35 show that they are connected to an NB7V33M 10GHz clock.

Pins 43 and 44 show that they are connected to a 122.88MHz  VCXO oscillator.

I have other reference documents from Texas Instruments that show the same clocks connected to the LMK04828B and we cannot figure out how Texas Instruments derived these are the clocks to use.  The LMK04828 pdf and DAC38RF83 documents is not clear on this either

On that same document page pins 49 and 50 are connected to the FPGA.  Why would you want to connect the SDCLKOUT output signals to the FPGA?

Thank you.

Randy Draper

RD Technologies

  • 0
    TI__Mastermind 28590 points

    Hello Randy,

    Randy Draper said:

    On page 5 of the tidrpe0.pdf document, pins 34 and 35 show that they are connected to an NB7V33M 10GHz clock.

    Pins 43 and 44 show that they are connected to a 122.88MHz  VCXO oscillator.

    The LMK04828 has multiple use cases.  Dual Loop Jitter Cleaner, single loop clock generator, and distribution.

    In dual loop jitter cleaner mode (see Fig 17 of datasheet), CLKin0, 1, or 2 allow input to PLL1 which uses an external VCXO for input to OSCin.  OSCin provides the feedback clock to PLL1 and the reference to PLL2 which allows the internal VCO to lock and provide output clocks.

    Now the LMK0482x hasn't been updated with more simplified block diagrams of possible use cases, but if you look at the LMK04808 datasheet (similar to LMK0482x but no JESD204B support) on figure 17, you will see OSCin is used as the reference to PLL2 and the internal VCO locks to the reference.  Finally figure 19 illustrates the clock distribution case where CLKin1 can drive the outputs direct.  Up to 3.1 GHz is allowed at CLKin1(Fin) in this mode.

    Hope that helps.

    Randy Draper said:
    On that same document page pins 49 and 50 are connected to the FPGA.  Why would you want to connect the SDCLKOUT output signals to the FPGA?


    In JESD204B, all logic devices and converters get a SYSREF so that they can have their LMFC's reset.

    73,
    Timothy