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Manual CDCE913 coefficient calculation

Thomas Rudloff
Prodigy 185 points

Other Parts Discussed in Thread: CDCE913, CDCS503, CDCE62005, CDCM61001, CDCE62002, CDC7005, CDCE72010, CDCM61002, CDCM7005

It looks to me, that the NI software is limited and I need to calculate lots of values because I need a larger frequency range than the pull range of the VCXO for an USB device (1000ppm by USB spec). So I will meassure the frequency relation and setup the CDCE913 with the appropriate values to be able to lock.

I asume fosc = (q + r / n) / 2 ^ p * fin and would like to get confirmation or corrections before trying to hack this out.

 

Thanks in advance

Thomas

  • 0
    TI__Expert 5725 points

    Thomas,

    I can help you to calculate the setups to go from one frequency to another in a fixed frequency step.  

    Please let me know initial frequency and final frequency and minimum delta between frequencies  so I can provide all setups needed to achieve this in a text file.

    Best regards,

    Mariajose

     

     

  • 0 in reply to mapefer3
    Prodigy 185 points

    Hi Mariajose,

    I did not decide the crystal frequency yet. Preferable would be 24MHz, so I can use a pass through on Y1 for USB clock. But this crystal might be more expensive than a 27MHz one often used for DVB/DVD clocking. Do you know were I can buy pullable crystals? Preferable in Germany or with affordable shipping cost like Mouser or DigiKey. I ordered AT cut types from RS-Components but do not know yet whether they will work.

    There are two output frequencies required: 24.576MHz for the 48ksps rate and multiples and 22.5792MHz for the 44.1ksps rate and multiples.


    Preferable stepping would be 25ppm since I am not able to change the frequency once I locked. This needs to cover a range of +/- 1000ppm as specified by USB.

    Because there are 81 settings per frequency I should solve the crystal challenge before dealing with that much data.

    I' ll come back on this.

    I saw you are familiar with the CDCS50x chips. Could I use a CDCS503 to de-jitter a simple DDS based on a phase accumulator? What timing resolution would I need to generate twice the above mentioned frequencies (because of the CDCS503 frequency limitations) in 4x mode?

     

    Thanks

    Thomas

  • 0 in reply to Thomas Rudloff
    TI__Expert 5725 points

    Hi Thomas,

     

    Did you take a look at the application’s note http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=scaa088 ? Is this similar to what you would like to achieve?

     

    What is the purpose of reprogramming the output frequency via I2C?

     

    +/-1000ppm is a big pullability range for a XTAL. Typical pullability ranges are in the range of 250ppm, fixed by the ratio between the motion capacitance and the shunt capacitance of the XTAL. I am currently checking with NDK if they provide XTALs with pullability to distributors. There is a post that might be of interest regarding this: http://e2e.ti.com/support/clocks/f/48/t/56234.aspx

     

    The CDCS503 will not clean the jitter of the input clock. There are high performance jitter cleaners that would (CDCM7005, CDC7005, CDCE72010, CDCE62005, CDCE62002, CDCM61001, CDCM61002).

    Please let me know more about the requirements for the jitter cleaner, what is the input frequency and the output frequencies to be achieved, also about the rms jitter targeted, and also integration bandwidths.

     

    Would it be possible to get more details about the application?

    Best regards,

    Mariajose

     

     

  • 0 in reply to mapefer3
    Prodigy 185 points

    Hi Mariajose,

    I know the app note and this is exactly what I want to do. With one exception: I do not have a word clock. The best I have is a 8kHz High Speed USB SOF (start of frame). The problem is USB allows a deviation of 1000ppm, but I do not expect the frequency to change that much over time. The idea is to measure the SOF frequency at plug in time and set the PLL according to this measurement. After this I will be able to lock and track deviations from the initial frequency. I will put the phase comparator in a small CPLD, which I need anyway to convert the output of the DMA channel to a serial stream. Either SPDIF or I2S.

    The USB controller needs a clock of 24MHz with, of course, a precission of 1000ppm. I will be much better, even though I am pulling, because of the initial adjustment.

     

    Consumer SPDIF allows 2000ppm deviation what falls in the spec. For AES I would need a sample rate converter to archive 50ppm precision required by the spec.

    The problem is that cheap PCs most likely are not precise enough to fall in the pull range of a standard VCXO and might cause a lot of trouble.

    An alternative would be to use a DDS and cleanup the clock. But this requires very much more effort than a simple phase comparator.

    Thanks

    Thomas

  • 0 in reply to mapefer3
    Prodigy 230 points

    I noticed the link to the thread I started and wanted to mention that I found a better solution, which I detail in a new post at the end of that thread.  Basically I found a CDCE9xx chip built into a package with a matching crystal for about the same footprint as the CDCE9xx itself...

  • 0 in reply to mapefer3
    Prodigy 15 points

    Hi

    I'm using cdce913, I have Fin and fout values,I want to know the pdiv,n,q,r,p val without using ti pro tool,i want to know these values manually.