LMK04826: Supply current

Hello,

I assumed dual loop, that tracking was off, one CLKin enabled.
I also changed from Divider only to Divider + DCC+ HS which is required for /1 mode on the two outputs set to /1.
I assumed an emitter resistor of 240 ohm is being used for all LVPECL outputs.
I also assumed SYSREF pulser is being used.

For this case I estimate typical current to be 704 mA.  Worst case, we typically use +15 or +20%; for +20% case this is 845 mA.

Note that during SYNC to align internal dividers the DDLY_PD must = 0 for assured alignment of clocks.  This will consume an extra approx 44 mA.  Also, when SYSREF_CLR = 1, there will be an extra 20 mA.  For the LVPECL outputs, assuming 240 ohms emitter resistor about 35 mW of power is dissipated externally for each output.  This will result in about 245 mW for all 7 outputs.

After using SYSREF, it is possible to power down SYSREF related block for a savings of 151 mA.

Please see attached file for your reference/adjustment.

4722.icc quick calculator, TT-2016-04-27_e2e, for 2017-02-22 question.xlsx

73,

Timothy

Hello Toshiyuki-san,

Please find the attachment related to max icc per pin.  Unfortunately based on configuration I do not have the expected Icc per pin, except that I expect the current associated with clock outputs, the divider, mux, outputs to come from the Vcc_CG# pins, and then the other PLL/VCO related pins from the other pins.

If necessary, I should be able provide an estimate by end of next week.

LMK0482x_WorstCaseICCperVCCpin_20170222_e2e.xls

Hello Toshiyuki-san,

We've collected some data on this.  Especially because they are using SYSREF, there are several modes or stages of operation possible.  For example, after performing synchronization it is possible to power down all the SYSREF outputs.

I used 240 ohm emitter resistors for the LVPECL outputs.  Using lower values will increase current in Vcc#_CG?.

See measurements below and attached.  Because they are using SYSREF, there are several stages of programming.  Even with digital delay on device clocks, there can be power savings by powering down the digital delay function after initial SYNC.

73,
Timothy

*Vcc5_DIG icc will increase for current source via Status_LD1 pin.  For example if an LED is driven by this pin.  If using an LED, consider setting output polarity to cause steady state condition to show LED off.  On the eval board this was an extra ~4 mA.
**Vcc10_PLL2 icc will increase for current source via Status_LD2 pin.  For example if an LED is driven by this pin.  If using an LED, consider setting output polarity to cause steady state condition to show LED off.  On the eval board this was an extra ~4 mA.

user case LMK04826 pin icc measurements.xlsx