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LMK03318: CodeLoader4 setting data

Satoshi
Guru 19655 points
Part Number: LMK03318


Customer is made attached below register for LMK03318 by CodeLoader4.

6052.LMK03318_Register.xlsx

LMK03318.zip

Please let me know about attached EXCEL data.

①About register data for filled yellow point.

　What are these register meaning? 

　I didn't find information by datasheet.

②About the point of question① 

　What should I set these register? (For example, do not write, write the data by CodeLoader4 output...)

③Data mismatching

　When customer set Read/Write below timing, R135 register was mismatching, is it no problem?

　・Write without Read only register (Filled green (or gray)) ⇒ Complete to write ⇒ Read these register

　　⇒R135 is mismatch： Write is 00hex, Read is d4hex

【Background】

・Customer problem for LMK03318 clock is not output, they are investigation in progress.

Best regards,

Satoshi

  • 0
    TI__Expert 4415 points

    Hi Satoshi,

    The missing addresses are Reserved for test/debug purposes and were not intended for customer use.

    It is prohibited to write to missing addresses, as it could cause unexpected device operation. They should be left to the default values and skipped when writing to the registers.

    R135 is a read only CRC byte and it is normal for it to not change if written to.

    I have also taken a look at the attached .mac config file and made a few changes (attached below). The only setting that is wrong is the PLL order should be set to 'Integer' instead of 3rd order (which is used for a fractional PLL). I made a few other recommended changes:

    -PLL closed loop wait time is increased to 0.3ms from 0.03ms. This will allow the PLL a little bit more time to lock.

    -PRIREF input frequency doubler is enabled and the PLL divider changed accordingly. Whenever possible, the doubler should be enabled to increase the phase detector frequency (up to the maximum of 150MHz) to improve phase noise performance.

    -AONAFTERLOCK enabled- this is a recommended default setting.

    LMK03318_TL.zip

    Regards,

    -Tim

  • 0 in reply to Tim Chao Li
    Guru 19655 points
    Tim-san

    Thank you for kind reply,
    So the other way, customer added Reset(PDN Low → High) wait time 10ms, clock was output.
    If there limitation for PDN Low→High timing, please let me know described point of the datasheet or application note.

    Best regards,
    Satoshi
  • 0 in reply to Satoshi
    TI__Expert 4415 points

    Hi Satoshi-san,

    It makes sense that after implementing a wait time of 10ms, the clock outputs are detected. 10ms is the max startup time of the device. See section 8.19: Power-on/Reset Characteristics of the datasheet on page 14 (also reproduced below):

    Regards,

    -Tim