LMK04828: design verifcation

David Siksik

Part Number: LMK04828

Hello,

I would like to use the LMK04828 as PLL and clock driver to all the JESD204B clocks and sysref's in my card.

The LMK04828 will get 108M in OSCin input pin and with the use of only PLL2 the device will drive 135M clock and sysref.

I will not use an external VCXO. PLL1 will be dsabled.

I designed the system with TICS software.

Can you please tell me if the attached TICS design in OK?

Thank you,

David

over 9 years ago

0 Timothy T over 9 years ago

TI__Mastermind 28590 points

Hello David,

You will need to program the VCO to operate in a valid frequency range for VCO1 or VCO0. Right now it is not valid at 135 MHz. I also think you will want to design the PLL2 phase detector frequency to be as large as possible.

I used the Clock Design Tool to enter 108 MHz as reference and 135 MHz as output. This solved for you to use VCO0 at 2430 MHz with PLL2 R = 2 for a PDF frequency of 54 MHz. PLL2_N = 15 and PLL2_Prescaler = 3. So basically 54 MHz * (15*3) = 2430 MHz.
Now program a clock output divider to 18, 2430 / 18 = 135 MHz.

73,
Timothy

0 David Siksik over 9 years ago in reply to Timothy T

Prodigy 215 points

Hello Timothy
Thank you for your fast response. Is that correct to say that in this case the following points?
1. It will be possible to drive the 108MHz clock in OSCin pin (CLKin0 and CLKin1 will be left unconnected).
2. I will not need any external VCXO.
3. I will not use PLL1 so in can be powered down without loop filter (CPout1 can be left unconnected) .
Thank you,
David

0 Timothy T over 9 years ago in reply to David Siksik

TI__Mastermind 28590 points

All 3 points are correct.

Keep in mind, always apply power to every Vcc even though you are powering down PLL1.

73,
Timothy

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LMK04828: design verifcation