LMK04828BEVM: How to deal with the SYSREF and DEVICE clock of DAC39J84

An liu

Part Number: LMK04828BEVM
Other Parts Discussed in Thread: LMK04828

The datasheet of DAC39J84 points out that the setup time and hoId time is 50ps. And in my design I chose LMK04828b as clock source and used fixed digital delay mode to adjust the relationship between sysref

clock and device clock.

The total delay time of SYSREF clock is (X+Y)/(frequency of VCO), where X is the value of register13C and 13D, Y is the value of register104/10C/114/11C/124/12C/134.

The total delay time of Device clock is Z/ (frequency of VCO), where Z is the value of register101/109/111/119/121/129/131.

In my design, frequency of VCO is 2400MHz, sysref is 9.375MHz, and device clock of FPGA is 150MHz, device clock of DAC39J84 is 600MHz.

And no matter what value I config the value of X, Y, Z, I can't meet the requirement of 50ps. And the delay time of SYSREF clock is always longer than the Device clock for the X is at least 8.

Can you help me? How to meet the relationship requirement between sysref clock and device clock .

over 8 years ago

0 Shawn Han over 8 years ago

TI__Genius 9920 points

Hi An,
I think you have generate SYSREF by SYNC operation. All SYSREF and device clocks had been synchronized.
Normally, deivce clock rising edge would sampling SYSREF high logic.
The target is to get setup time (from SYSREF rising edge to deivce clock rising edge) > 50ps, and hold time (from device clock rising edge to SYSREF falling edge ) > 50ps. In your case, device clock period is 1/150 MHz = 6667 ps. There are enough room to tune delay. If the problem is still there, you could post LMK04828 register value and scope capture.

Best Regards,
Shawn Han

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LMK04828BEVM: How to deal with the SYSREF and DEVICE clock of DAC39J84