Other Parts Discussed in Thread: DAC39J84
Hi deer TI
I use LMK04828 to supply device clock and SYSREF to DAC39J84 on my own board. There are some questions about the setup time between device clock and SYSREF.
- My JESD204B configuration is LMF = 841 HD =1 k =32. My device clock = 600MHz, SYSREF = 9.375MHz. The frequency of device clock is much higher than SYSREF. There is no doubt that SYSREF will be sampled by device clock. In other words even though the first rise edge of device clock doesn't sample the SYSREF ' high level. There must be a rise edge of device clock can sample the SYSREF ' high level after the first one. Is it necessary to set the setup time between Device clock and SYSREF.(As the data sheet of DAC39J84 setup time =50ps)
- I found the rise time of SYSREF is a little along on the oscilloscope. When I set the SYSREF_DDLY and the DCLKout_DDLY, whether I must compensate the rise time. How do I measure the setup time between the device clock and SYSREF? Where is the origin of SYSREF to measure the setup time between the device clock and SYSREF. The first point of non zeros point of the first point getting to 90% of the high level? When the device clock is a sine waveform. How can I judge the point corresponding to the rise edge of the sine waveform.
Regards
Zhipeng
