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CDCM6208: Output Duty Cycle

Michael Slade
Prodigy 30 points

Part Number: CDCM6208

In the Output Characteristics tables [7.17 LVDS for example] the Output Duty Cycle is specified as:

Test Conditions: Not in bypass mode, Y[3:0] = 47.5% - 52.5%, Y[7:4] = 45% - 55%

1) Should I take this to mean regardless of the output divider setting, the duty cycle will be in this range?

2) What is the duty cycle when it is in bypass mode?

Thank you,
Michael

  • 0
    TI__Mastermind 32575 points

    Hello,

    1) Correct, there is duty cycle correction on PLL output clocks.

    2) In bypass mode, the output duty cycle would be based on the clock input duty cycle +/-5% (typical ODC variation), as there is no duty cycle correction in bypass mode.

    Regards,
    Alan