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LMK04828: PLL2_DLD is always low for OSCIN = 62.5MHz

Sowri Rekha Devanaboyina
Prodigy 70 points
Part Number: LMK04828
Other Parts Discussed in Thread: CODELOADER

Hello Experts,

My PLL2_DLD is always low when OSCIN = 62.5MHz. Please check my register configuration and help if I miss any thing. 

SPI_Write(1, 0x0160, 0x00);

SPI_Write(1, 0x0161, 0x01); //PLL2_R = 1

SPI_Write(1, 0x0162, 0x40); //PLL2_P = 2 , OSCin frequency 0 to 63 MHz

SPI_Write(1, 0x0164, 0x00); 

SPI_Write(1, 0x0165, 0x0C); //PLL2_N_CAL = 12

SPI_Write(1, 0x0167, 0x00);

SPI_Write(1, 0x0168, 0x18); //PLL2_N = 24

Thanks,

Rekha

  • 0
    TI__Mastermind 28560 points
    The above looks good, but do you have a full programming of the device? Ideally in a codeloader (.mac) or TICS Pro (tcs) file?

    Is the PLL2 locked and simply failing to report lock or actually unlocked?
    - What is the CPout2 voltage?

    Does PLL2_DLD report locked for some other conditions?
    - Some issues off the top of my head include OSCin_PD = 1 (0x140[4] = 1)
    - If you have a VCO_MUX [0x138, bits 5:6] not set to 0x01 for VCO1
    - Also PLL2_CP_POL[0x169, bit 2] should be 0 for negative cp current.

    For debugging, I suggest programming the PLL1_LD_MUX = 0x12 (PLL2_R/2) (page 82); and PLL2_LD_MUX = 0x0e (PLL2_N/2) (page 0x16e); but sure to also program PLLX_LD_TYPE as needed, typically 0x03 (Output push/pull). You should see half the phase detector frequency at these pins from the PLL2 R or PLL2 N divider path. If you don't see this, this can help debug what path is having an issue.

    73,
    Timothy