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LMK01010: Part-to-Part Skew and sync

Part Number: LMK01010
Other Parts Discussed in Thread: LMK04828

Hello,

1) I need to know the typical and max part-to-part skew on this part. This is critical. I'm using 8 parts in parallel and crucially dependent on this parameter.

2) I will be running 8 of these parts in parallel and will be using the SYNC function. If I'm using an output with bypassed selected and use the SYNC pin to synchronize all parts and then when to switch from bypassed to divide-by-2, will I still have synchronization in the divide-by-2? The reason is because I want to use the bypassed mode to check the clock phase, then switch to divide-by-2 and check its phase relative to another parts divide-by-2.

3) If I use "clk en" to turn off a channel, will I lose SYNC from a divide-by-2 mode when I enable the channel again?

  • Hello,

    What is your frequency you are inputting to LMK01010 for fanout or div-by-2?

    The SYNC pin is a CMOS pin and we don't have a setup and hold time specified for the SYNC pin to reset the dividers. So from a multi-part perspective, this is also critical. For high speeds, the LMK01010 CMOS SYNC input pin may not be acceptable. I don't have the data at this time to state either way.

    The LMK0482x can also be used for fan-out/divide. The CLKin0 signal path can be used to provide a SYNC reset to the dividers and the CLKin0 can behave as a high speed SYNC path. I don't have min/max setup time for this either at the moment, but this would be a good solution for high frequency use-case.

    I think the divider gets powered down in bypass mode, so that would result in a loss of synchronization.

    EN_CLKoutX = 0 (Disabled) will power down the output divider, so again a loss of synchronization.  If you wanted to stop the output without losing synchronization, on LMK0482x you could power down the output and keep the divider running.

    What is your timeline for this information?

    73,
    Timothy

  • Thanks for your reply Timothy,

    What is your frequency you are inputting to LMK01010 for fanout or div-by-2?

    From DC to 1.6GHz. 

    The SYNC pin is a CMOS pin and we don't have a setup and hold time specified for the SYNC pin to reset the dividers. So from a multi-part perspective, this is also critical. For high speeds, the LMK01010 CMOS SYNC input pin may not be acceptable. I don't have the data at this time to state either way.

    The LMK0482x can also be used for fan-out/divide. The CLKin0 signal path can be used to provide a SYNC reset to the dividers and the CLKin0 can behave as a high speed SYNC path. I don't have min/max setup time for this either at the moment, but this would be a good solution for high frequency use-case.

    I don't understand. 

    I think the divider gets powered down in bypass mode, so that would result in a loss of synchronization.

    ok

    EN_CLKoutX = 0 (Disabled) will power down the output divider, so again a loss of synchronization.  If you wanted to stop the output without losing synchronization, on LMK0482x you could power down the output and keep the divider running.

    What is your timeline for this information?

    I need this information in a couple days. I can get around the SYNC problem, but for the part-to-part skew. Do you have any educated guesses?

     

    Thank you for your reply,

    Kevin

  • Hello Kevin,

    Since you are going to 1.6 GHz, I'm not sure that by using the CMOS SYNC pin on the LMK01010 you will be able to assure synchronization across all devices over PVT to have /2 phases aligned. Sounds like that is important for your application.

    We have another device LMK04828 that can be used for fan-out/divide, but includes a high speed path via CLKin0 which could be used to reset the dividers at higher frequencies. Is this something that you've already finalized your design on for LMK01010?

    73,
    Timothy
  • Hi Timothy,

    LMK0482x series look really good. What is the part to part skew on these? I have not finalized my design yet... 

  • Hello Kevin,

    I'm sorry at this time I don't have an answer for part to part variation in distribution mode of LMK0482x.

    The datasheet does have a CLKin0 --> SDCLKout propagation delay of 650 ps typical. If I assume this number is similar for CLKin1 --> DCLKout (I would need to confirm). And assume a PVT variation of +/- 30% with one device at -30% and another at +30%, this would suggest a part to part skew of 390 ps. However I think this is quite conservative as I wouldn't expect the voltage and temp to be at extremes of each other for the two devices.

    73,
    Timothy
  • Thank you for your reply Timothy. One question.

    I want to use a DCLKoutx with Analog Delay with divide = 1. The datasheet says divide by 1 is not valid for two cases below:

    Not valid if DCLKoutX_MUX = 0, Divider only. Not valid if DCLKoutX_MUX = 3 (Analog Delay + Divider) and DCLKoutX_ADLY_MUX =
    0 (without duty cycle correction/halfstep).

    Does this imply that I can use DCLKoutX_Mux = 3 and DCLKoutX_ADLY_MUX = 1 and use divide by 1?