Other Parts Discussed in Thread: TMS320C6657
I am using this part to supply a 100 MHZ LVDS core clock to a Keystone DSP.
The keystone DSP (TMS320C6657) data sheet states that the clock driver should be in high impedance until the core voltage is up. This clock driver data sheet does not state the behavior of the LVDS clock outputs before and during the power up sequence - are they floating? Grounded?
To this end, my plan was to either
1. disable the clock driver power supply until the DSP core voltage is up (but is this clock driver high impedance if no power voltage?)
or
2. allow the clock driver to power up simultaneously with the DSP core voltage. There will be a millisecond or so where the clock driver is powered up and the DSP core is not, but I don't know how immediately this clock driver will start fanning out the input clock.
Not enough information in the clock driver data sheet to determine best course of action.
